e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
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"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
9eb3f00406
Now that PR11464 is fixed, reapply the patch to fix PR11464,
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merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.
llvm-svn: 146932
2011-12-20 00:12:26 +00:00
5e3bd9727a
fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
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llvm-svn: 146929
2011-12-20 00:03:52 +00:00
3bfaefe9e7
Move tests to FileCheck.
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llvm-svn: 146923
2011-12-19 23:26:44 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
37c45db189
Add a test case for r146900.
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llvm-svn: 146901
2011-12-19 20:24:28 +00:00
db47e0c49d
Add patterns for matching immediates whose lower 16-bit is cleared. These
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patterns emit a single LUi instruction instead of a pair of LUi and ORi.
llvm-svn: 146900
2011-12-19 20:21:18 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
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rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
2a232d81f6
Remove definitions of double word shift plus 32 instructions. Assembler or
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direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
llvm-svn: 146893
2011-12-19 19:44:09 +00:00
3c9f336361
Remove the restriction on the first operand of the add node in SelectAddr.
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This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
llvm-svn: 146888
2011-12-19 19:28:37 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
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llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
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There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
d6cb7649d8
Allow inlining of functions with returns_twice calls, if they have the
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attribute themselve.
llvm-svn: 146851
2011-12-18 20:35:43 +00:00
5e5bee4c52
Revert 146728 as it's causing failures on some of the external bots as well as
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internal nightly testers. Original commit message:
By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.
llvm-svn: 146838
2011-12-17 22:19:53 +00:00
8b3deabd2d
Revert r146822 at Pete Cooper's request as it broke clang self hosting.
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Hope I did this correctly :)
llvm-svn: 146834
2011-12-17 19:48:52 +00:00
eadf124d2b
SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
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For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/10554090>
llvm-svn: 146822
2011-12-17 06:32:38 +00:00
3c2848ea31
Deleting the json-bench-test until I understand why it is flaky.
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llvm-svn: 146821
2011-12-17 06:29:32 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
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llvm-svn: 146805
2011-12-17 01:25:34 +00:00
d3df3d3527
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
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asm parsing and testcase.
llvm-svn: 146801
2011-12-17 01:14:52 +00:00
da07b3ad42
Make sure that the lower bits on the VSELECT condition are properly set.
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llvm-svn: 146800
2011-12-17 01:08:46 +00:00
518cda42b9
The powers that be have decided that LLVM IR should now support 16-bit
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"half precision" floating-point with a first-class type.
This patch adds basic IR support (but not codegen support).
llvm-svn: 146786
2011-12-17 00:04:22 +00:00
27886c6c1e
When recursing for the original size of a type, stop if we are at a
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pointer or a reference type - we actually just want the size of the
pointer then for that.
Fixes rdar://10335756
llvm-svn: 146785
2011-12-16 23:42:45 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
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The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
9ca2e7293b
Hexagon: Fix a nasty order-of-initialization bug.
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Reenable the tests.
llvm-svn: 146750
2011-12-16 19:08:59 +00:00
2c899a181c
Adds a JSON parser and a benchmark (json-bench) to catch performance regressions.
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llvm-svn: 146735
2011-12-16 13:09:10 +00:00
3fdf98c60f
By popular demand, link up types by name if they are isomorphic and one is an
...
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large app.
llvm-svn: 146728
2011-12-16 08:36:07 +00:00
a4d411cb1b
Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes.
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llvm-svn: 146726
2011-12-16 08:06:31 +00:00
561dade58d
[asan] add a test for instrumenting globals
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llvm-svn: 146718
2011-12-16 01:28:19 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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llvm-svn: 146699
2011-12-15 22:56:33 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
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llvm-svn: 146691
2011-12-15 22:27:11 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
918f976e66
Set specific target cpu for testcase.
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llvm-svn: 146678
2011-12-15 20:22:34 +00:00
2d6d3a2f96
Added test case for r146671.
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llvm-svn: 146675
2011-12-15 19:56:07 +00:00
750366f014
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
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llvm-svn: 146666
2011-12-15 17:59:23 +00:00
ef7b2f2532
Fix test.
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llvm-svn: 146642
2011-12-15 04:52:47 +00:00
a45ab503f6
Make constant folding for GEPs a bit more aggressive.
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llvm-svn: 146639
2011-12-15 04:33:48 +00:00
2ec824966d
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
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llvm-svn: 146630
2011-12-15 02:07:20 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
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rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
b33c297f14
Added InstCombine for "select cond, ~cond, x" type patterns
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These can be reduced to "~cond & x" or "~cond | x"
llvm-svn: 146624
2011-12-15 00:56:45 +00:00
16ad2905a3
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
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llvm-svn: 146621
2011-12-15 00:50:34 +00:00
75d7d5e988
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
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into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
llvm-svn: 146610
2011-12-14 23:49:11 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
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llvm-svn: 146605
2011-12-14 23:25:46 +00:00
c268688643
Do not sink instruction, if it is not profitable.
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On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar 10266272.
llvm-svn: 146604
2011-12-14 23:20:38 +00:00
ad41ab5015
Improve the implementation of .incbin directive by replacing a loop by using
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getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
llvm-svn: 146599
2011-12-14 22:34:45 +00:00
e0ced62119
LSR: Fold redundant bitcasts on-the-fly.
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llvm-svn: 146597
2011-12-14 22:07:19 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
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Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
109f25c966
Add the .incbin directive which takes the binary data from a file and emits
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it to the streamer. rdar://10383898
llvm-svn: 146592
2011-12-14 21:47:48 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
Jim Grosbach