Commit Graph

191667 Commits

Author SHA1 Message Date
Justin Lebar dd11c8fb0d Fix SFINAE in JSON.h constructor.
Summary:
This used std::enable_if without referencing ::type.  Changed to use
std::enable_if_t.

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74381
2020-02-11 07:38:42 -08:00
Florian Hahn aadb635e04 [SCCP] Remove forcedconstant, go to overdefined instead
This patch removes forcedconstant to simplify things for the
move to ValueLattice, which includes constant ranges, but no
forced constants.

This patch removes forcedconstant and changes ResolvedUndefsIn
to mark instructions with unknown operands as overdefined. This
means we do not do simplifications based on undef directly in SCCP
any longer, but this seems to hardly come up in practice (see stats
below), presumably because InstCombine & others take care
of most of the relevant folds already.

It is still beneficial to keep ResolvedUndefIn, as it allows us delaying
going to overdefined until we propagated all known information.

I also built MultiSource, SPEC2000 and SPEC2006 and compared
sccp.IPNumInstRemoved and sccp.NumInstRemoved. It looks like the impact
is quite low:

Tests: 244
Same hash: 238 (filtered out)
Remaining: 6
Metric: sccp.IPNumInstRemoved

Program                                        base     patch    diff
 test-suite...arks/VersaBench/dbms/dbms.test     4.00    3.00  -25.0%
 test-suite...TimberWolfMC/timberwolfmc.test    38.00   34.00  -10.5%
 test-suite...006/453.povray/453.povray.test   158.00  155.00  -1.9%
 test-suite.../CINT2000/176.gcc/176.gcc.test   668.00  668.00   0.0%
 test-suite.../CINT2006/403.gcc/403.gcc.test   1209.00 1209.00  0.0%
 test-suite...arks/mafft/pairlocalalign.test    76.00   76.00   0.0%

Tests: 244
Same hash: 238 (filtered out)
Remaining: 6
Metric: sccp.NumInstRemoved

Program                                        base    patch     diff
 test-suite...arks/mafft/pairlocalalign.test   185.00  175.00  -5.4%
 test-suite.../CINT2006/403.gcc/403.gcc.test   2059.00 2056.00 -0.1%
 test-suite.../CINT2000/176.gcc/176.gcc.test   2358.00 2357.00 -0.0%
 test-suite...006/453.povray/453.povray.test   317.00  317.00   0.0%
 test-suite...TimberWolfMC/timberwolfmc.test    12.00   12.00   0.0%

Reviewers: davide, efriedma, mssimpso

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D61314
2020-02-11 15:24:15 +00:00
Sjoerd Meijer 6b0ed508fa [ARM][MVE] Tail-Predication: recognise (again) active lanes IR pattern
A small IR change in calculating the active lanes resulted in no longer
recognising tail-predication. Now recognise both an 'add' and 'or' in
the expression that calculates the active lanes.

Differential Revision: https://reviews.llvm.org/D74394
2020-02-11 15:18:18 +00:00
Alexandre Ganea faace36508 [Clang][Driver] After default -fintegrated-cc1, make llvm::report_fatal_error() generate preprocessed source + reproducer.sh again.
Added a test for #pragma clang __debug llvm_fatal_error to test for the original issue.
Added llvm::sys::Process::Exit() and replaced ::exit() in places where it was appropriate. This new function would call the current CrashRecoveryContext if one is running on the same thread; or call ::exit() otherwise.

Fixes PR44705.

Differential Revision: https://reviews.llvm.org/D73742
2020-02-11 10:17:30 -05:00
Andrew Wei db875f6655 [RISCV] Optimize seteq/setne pattern expansions for better code size
ADDI(C.ADDI) may achieve better code size than XORI, since XORI has no C extension.
This patch transforms two patterns and gets almost equivalent results.

Differential Revision: https://reviews.llvm.org/D71774
2020-02-11 22:45:15 +08:00
Kadir Cetinkaya 42f8b915eb
Revert "[DSE] Add first version of MemorySSA-backed DSE (Bottom up walk)."
This reverts commit d0c4d4fe09.

Revert "[DSE,MSSA] Move more passing test cases from todo to simple.ll."

This reverts commit 02266e64bb.

Revert "[DSE,MSSA] Adjust mda-with-dbg-values.ll to MSSA backed DSE."

This reverts commit 74f03e4ff0.
2020-02-11 15:34:48 +01:00
Simon Pilgrim fa620fc8e2 [X86] combineConcatVectorOps - reuse IsSplat and remove duplicate code. NFC. 2020-02-11 13:37:57 +00:00
Sanjay Patel a2a0f9a43a [VectorCombine] remove unused debug counter; NFC
The variable was added to the initial commit via copy/paste of existing
code, but it wasn't actually used in the code. We can add it back with
the proper usage if/when that is needed.
2020-02-11 08:24:07 -05:00
Simon Pilgrim 11c16e7159 [X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SSSE3 targets
Without PSHUFB we are better using ROTL (expanding to OR(SHL,SRL)) than using the generic v16i8 shuffle lowering - but if we can widen to v8i16 or more then the existing shuffles are still the better option.
2020-02-11 12:21:03 +00:00
Alexey Lapshin cc9b4fb6c9 [Debuginfo][NFC] Rename error handling functions using the same pattern.
Summary:
That patch is extracted from https://reviews.llvm.org/D74308.
Currently there are two patterns to name error handling functions:
using "Callback" and "Handler". This patch uses "Handler" for all
usage places.

Reviewers: jhenderson, dblaikie, probinson, aprantl

Reviewed By: jhenderson, dblaikie

Subscribers: hiraditya, llvm-commits

Tags: #llvm, #debug-info

Differential Revision: https://reviews.llvm.org/D74354
2020-02-11 14:50:53 +03:00
Mirko Brkusanin 5ba931a84a [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.
New intrinisics are implemented for when we need to port SIMD code from other
arhitectures and only load or store portions of MSA registers.

Following intriniscs are added which only load/store element 0 of a vector:
v4i32 __builtin_msa_ldrq_w (const void *, imm_n2048_2044);
v2i64 __builtin_msa_ldr_d (const void *, imm_n4096_4088);
void __builtin_msa_strq_w (v4i32, void *, imm_n2048_2044);
void __builtin_msa_str_d (v2i64, void *, imm_n4096_4088);

Differential Revision: https://reviews.llvm.org/D73644
2020-02-11 11:47:30 +01:00
Kerry McLaughlin e7755f9e4f [AArch64][SVE] Add SVE2 intrinsics for complex integer dot product
Summary:
Implements the following intrinsics:
 - @llvm.aarch64.sve.cdot
 - @llvm.aarch64.sve.cdot.lane

Reviewers: sdesmalen, efriedma, dancgr, c-rhodes, rengolin

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73687
2020-02-11 10:28:31 +00:00
OCHyams 35e0ab647b [DebugInfo][NFC] Fixup the UserValue methods to use FragmentInfo
Fixup the UserValue methods to use FragmentInfo instead of DIExpression because
the DIExpression is only ever used to get the to get the FragmentInfo. The
DIExpression is meaningless in the UserValue class because each definition point
added to a UserValue may have a unique DIExpression.

Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D74057
2020-02-11 10:20:24 +00:00
OCHyams 3aa33fde03 [DebugInfo][NFC] Rename the class DbgValueLocation to DbgVariableValue
Rename the class DbgValueLocation to DbgVariableValue and instances from Loc to
DbgValue. These names better express the new semantics introduced in D74053.

The class previously represented a { Location } only. It now represents a
{ Location, DIExpression } pair which together describe a value.

Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D74055
2020-02-11 10:20:24 +00:00
OCHyams 1e40799324 [DebugInfo] Teach LDV how to handle identical variable fragments
LiveDebugVariables uses interval maps to explicitly represent DBG_VALUE
intervals. DBG_VALUEs are filtered into an interval map based on their {
Variable, DIExpression }. The interval map will coalesce adjacent entries that
use the same { Location }.  Under this model, DBG_VALUEs which refer to the same
bits of the same variable will be filtered into different interval maps if they
have different DIExpressions which means the original intervals will not be
properly preserved.

This patch fixes the problem by using { Variable, Fragment } to filter the
DBG_VALUEs into maps, and coalesces adjacent entries iff they have the same
{ Location, DIExpression } pair.

The solution is not perfect because we see the similar issues appear when
partially overlapping fragments are encountered, but is far simpler than a
complete solution (i.e. D70121).

Fixes: pr41992, pr43957
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D74053
2020-02-11 10:20:24 +00:00
Georgii Rymar 60e9b5888f [llvm-readobj][test] - Add a test for --elf-cg-profile option.
This adds a test to document --elf-cg-profile  option we have.
I am going to refactor this area, and this patch is mostly to
create a base for a follow-up change.

Differential revision: https://reviews.llvm.org/D74115
2020-02-11 13:06:36 +03:00
Jay Foad b06a13f541 [AMDGPU] Fix non-deterministic iteration order
Summary:
As far as I know this did not affect code generation, but it did affect
the order of -debug-only=si-wqm output and the naming of autonamed
values in -print-after=si-wqm output.

Reviewers: arsenm, rampitec, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, mgrang, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74317
2020-02-11 09:19:30 +00:00
Craig Topper 798305d29b [X86] Custom lower ISD::FP16_TO_FP and ISD::FP_TO_FP16 on f16c targets instead of using isel patterns.
We need to use vector instructions for these operations. Previously
we handled this with isel patterns that used extra instructions
and copies to handle the the conversions.

Now we use custom lowering to emit the conversions. This allows
them to be pattern matched and optimized on their own. For
example we can now emit vpextrw to store the result if its going
directly to memory.

I've forced the upper elements to VCVTPHS2PS to zero to keep some
code similar. Zeroes will be needed for strictfp. I've added a
DAG combine for (fp16_to_fp (fp_to_fp16 X)) to avoid extra
instructions in between to be closer to the previous codegen.

This is a step towards strictfp support for f16 conversions.
2020-02-10 22:01:48 -08:00
Kai Luo d4c7ade128 [NFC] Fix typo. 2020-02-11 13:58:35 +08:00
Fangrui Song 9f854c0489 [ELF][RISCV] Add R_RISCV_IRELATIVE
https://github.com/riscv/riscv-elf-psabi-doc/pull/131 assigned 58 to R_RISCV_IRELATIVE.

Differential Revision: https://reviews.llvm.org/D74022
2020-02-10 20:22:39 -08:00
Johannes Doerfert 5afd9fd916 [CodingStandards] Clarify C++ Standard Library usage
The existing wording leaves it unclear if C++ standard library data
structures should be preferred over custom LLVM ones, e.g., SmallVector,
even though common practice seems clear on the issue. This change makes
the wording more explicit and aligns it better with the code base.

Some motivating statistics:

```
ag SmallVector llvm/lib/ | wc
  8846   40306  901421
 ag 'std::vector' llvm/lib/ | wc
  2123    8990  214482

ag SmallVector clang/lib/ | wc
  3023   13824  281691
ag 'std::vector' clang/lib/ | wc
   719    2914   72817
```

Differential Revision: https://reviews.llvm.org/D74340
2020-02-10 20:30:00 -06:00
River Riddle 52086f802e [llvm][TableGen] Define FieldInit::isConcrete overload
Summary:
There are a few field init values that are concrete but not complete/foldable (e.g. `?`). This allows for using those values as initializers without erroring out.

Example:

```
class A {
  string value = ?;
}
class B<A impl> : A {
  let value = impl.value; // This currently emits an error.
  let value = ?;          // This doesn't emit an error.
}
```

Differential Revision: https://reviews.llvm.org/D74360
2020-02-10 18:04:58 -08:00
diggerlin 09d26b79d2 [NFC] Refactor the tuple of symbol information with structure for llvm-objdump
SUMMARY:

refator the std::tuple<uint64_t, StringRef, uint8_t> to structor

Reviewers: daltenty
Subscribers: wuzish, nemanjai, hiraditya

Differential Revision: https://reviews.llvm.org/D74240
2020-02-10 19:23:01 -05:00
David Blaikie 7b72c5835c DebugInfo: Avoid truncating addr_base to 32 bits
I'm /guessing/ this isn't terribly testable without a very large input
file. Even generated from a more compact assembly file, it's probably
best not to generate a giant temporary test file - if I'm wrong about
that/anyone has good suggestions for testing, I'm all ears!

Based on post-commit review feedback from Igor Kudrin on
eed0242330
2020-02-10 15:50:52 -08:00
Amara Emerson 067dd9c6b1 [GlobalISel][CallLowering] Use stripPointerCasts().
A downstream test exposed a simple logic bug with the manual pointer
stripping code, fix that by just using stripPointerCasts() on the value.

I don't think there's a way to expose this issue upstream.
2020-02-10 15:43:57 -08:00
Eric Christopher 7bba79ba0c Fix you->your typo. 2020-02-10 15:07:06 -08:00
Sanjay Patel b8ebc11f03 [EarlyCSE] avoid crashing when detecting min/max/abs patterns (PR41083)
As discussed in PR41083:
https://bugs.llvm.org/show_bug.cgi?id=41083
...we can assert/crash in EarlyCSE using the current hashing scheme and
instructions with flags.

ValueTracking's matchSelectPattern() may rely on overflow (nsw, etc) or
other flags when detecting patterns such as min/max/abs composed of
compare+select. But the value numbering / hashing mechanism used by
EarlyCSE intersects those flags to allow more CSE.

Several alternatives to solve this are discussed in the bug report.
This patch avoids the issue by doing simple matching of min/max/abs
patterns that never requires instruction flags. We give up some CSE
power because of that, but that is not expected to result in much
actual performance difference because InstCombine will canonicalize
these patterns when possible. It even has this comment for abs/nabs:

  /// Canonicalize all these variants to 1 pattern.
  /// This makes CSE more likely.

(And this patch adds PhaseOrdering tests to verify that the expected
transforms are still happening in the standard optimization pipelines.

I left this code to use ValueTracking's "flavor" enum values, so we
don't have to change the callers' code. If we decide to go back to
using the ValueTracking call (by changing the hashing algorithm
instead), it should be obvious how to replace this chunk.

Differential Revision: https://reviews.llvm.org/D74285
2020-02-10 17:25:34 -05:00
Ted Woodward 7683a084de Remove lit feature object-emission
Summary: The lit feature object-emission was added because Hexagon did not support the integrated assembler, so some tests needed to be turned off with a Hexagon target. Hexagon now supports the integrated assembler, so this feature can be removed.

Reviewers: bcain, kparzysz, jverma, whitequark, JDevlieghere

Reviewed By: JDevlieghere

Subscribers: mehdi_amini, hiraditya, steven_wu, dexonsmith, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73568
2020-02-10 15:57:56 -06:00
LLVM GN Syncbot f1ceda4bd5 [gn build] Port bb383ae612 2020-02-10 21:43:41 +00:00
Hiroshi Yamauchi bb383ae612 [CallPromotionUtils] Add tryPromoteCall.
Summary: It attempts to devirtualize a call on alloca through vtable loads.

Reviewers: davidxl

Subscribers: mgorny, Prazek, hiraditya, llvm-commits

Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71308
2020-02-10 13:43:16 -08:00
Martin Storsjö bc8e442188 [test] Disable the Passes/PluginsTest cases on windows with BUILD_SHARED_LIBS
The plugin expects to have undefined references to symbols exported
by the loading process, which isn't supported by shared libraries
on windows.

Differential Revision: https://reviews.llvm.org/D74042
2020-02-10 22:50:36 +02:00
Nico Weber e4e9e106b9 git bisect docs: formatting tweaks 2020-02-10 15:47:59 -05:00
Xiangling Liao 660b0d7f7b [AIX] Enable frame pointer for AIX and add related test suite
This patch:
   - enable frame pointer for AIX;
   - update some of red zone comments;
   - add/update testcases;

Differential Revision: https://reviews.llvm.org/D72454
2020-02-10 15:43:41 -05:00
Matt Arsenault f270da6bfc RegisterCoalescer: Add LaneMask to debug printing 2020-02-10 12:34:33 -08:00
Nico Weber 8116635e8b add GitBisecting to toctrees to try and placate the sphinx bot 2020-02-10 15:33:28 -05:00
Sterling Augustine 0bd48c3d4e [DebugInfo] Support file-level include directories when generating DWARFv5 LineTable prologues.
Differential Revision: https://reviews.llvm.org/D74249
2020-02-10 12:24:46 -08:00
Nico Weber c1adb88a31 git bisect docs: try to make commit ascii art show up 2020-02-10 15:18:58 -05:00
Sanjay Patel 0ad6e726ec [Transforms] add phase ordering tests for min/max/abs; NFC
Test that instcombine and early-cse can cooperate
to reduce sequences of select patterns that are not
composed of the same underlying instructions.

There's a bug in EarlyCSE (PR41083), and we can test
how much a possible fix (D74285) may affect optimization.
2020-02-10 15:14:46 -05:00
Sanjay Patel 62ce7e650a [InstCombine] fix use check when canonicalizing abs/nabs
We were checking for extra uses of the negated operand even
if we were not going to create it as part of this canonicalization.

This was showing up as a regression when we limit EarlyCSE as
proposed in D74285.
2020-02-10 14:57:37 -05:00
Sanjay Patel 93073e52b1 [InstCombine] add tests for abs with extra use of operand; NFC 2020-02-10 14:57:37 -05:00
diggerlin aa86311e62 [AIX][XCOFF] Support Mergeable2ByteCString and Mergeable4ByteCString
SUMMARY:
The patch is enable to support Mergeable2ByteCString and Mergeable4ByteCString

Reviewers: daltenty
Subscribers: wuzish, nemanjai, hiraditya

Differential Revision: https://reviews.llvm.org/D74164
2020-02-10 14:45:54 -05:00
Nico Weber 45c6c82e90 Add documentation on git bisecting across the MLIR merge
Differential Revision: https://reviews.llvm.org/D73988
2020-02-10 14:25:43 -05:00
Eric Christopher 102814b4d3 Continue removing llgo. 2020-02-10 10:33:58 -08:00
Florian Hahn d15325c9e0 [ValueLattice] Remove obsolete getConstantInt (NFC).
ConstantInt values are always represented as constant ranges with a
single element. getConstantInt is obsolete, as pointed out by @nikic
during D60581.

Reviewers: nikic

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D74329
2020-02-10 18:25:21 +00:00
Rachel Craik 1f55420065 [LoopCacheAnalysis]: Add support for negative stride
LoopCacheAnalysis currently assumes the loop will be iterated over in
a forward direction. This patch addresses the issue by using the
absolute value of the stride when iterating backwards.

Note: this patch will treat negative and positive array access the
same, resulting in the same cost being calculated for single and
bi-directional access patterns. This should be improved in a
subsequent patch.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D73064
2020-02-10 13:22:35 -05:00
Jonas Paulsson fcdb99e0b5 [SystemZ] Add a subtarget cache like some other targets already have.
Each function is with this compiled with the SystemZSubtarget initialized
from the functions attributes.

Review: Ulrich Weigand.

Differential Revision: https://reviews.llvm.org/D74086
2020-02-10 13:10:58 -05:00
Matt Arsenault 7af7b96a9b AMDGPU: Move R600 test compatability hack
Instead of handling the r600 intrinsics on amdgcn, handle the amdgcn
intrinsics on r600.
2020-02-10 10:02:06 -08:00
Simon Pilgrim f319074824 [X86] combineConcatVectorOps - combine X86ISD::PACKSS ops 2020-02-10 17:48:02 +00:00
Simon Pilgrim 74c0f98cf5 [X86] combineConcatVectorOps - combine X86ISD::VPERMI ops 2020-02-10 17:48:01 +00:00
Simon Pilgrim 2463b8c97d [X86] combineConcatVectorOps - combine VSHLI/VSRAI/VSRLI ops
Non-AVX512BW targets failed to concatenate 256-bit shifts back to 512-bits (split during 512-bit shuffle lowering as they don't have v32i16/v64i8 types).
2020-02-10 16:59:09 +00:00