5ea0a68115
AVX512: ktest implemantation
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Added tests for encoding.
Differential Revision: http://reviews.llvm.org/D11979
llvm-svn: 246439
2015-08-31 13:30:19 +00:00
98a045c978
AVX512: Add encoding tests for vscatter instructions
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Differential Revision: http://reviews.llvm.org/D11941
llvm-svn: 246431
2015-08-31 11:33:50 +00:00
8352a0ddf2
AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11528
llvm-svn: 243390
2015-07-28 06:53:28 +00:00
f2460112ad
Implemented encoding and intrinsics of the following instructions
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vunpckhps/pd, vunpcklps/pd,
vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11509
llvm-svn: 243246
2015-07-26 14:41:44 +00:00
a5b2e5e2a7
[X86][AVX512] add reduce/range/scalef/rndScale
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include encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D11222
llvm-svn: 242896
2015-07-22 12:00:43 +00:00
0f370936a0
AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.
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In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.
Differential Revision: http://reviews.llvm.org/D11134
llvm-svn: 242023
2015-07-13 13:26:20 +00:00
15820b072b
AVX-512: Implemented missing encoding for FMA scalar instructions
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Added tests for encoding
Differential Revision: http://reviews.llvm.org/D10865
llvm-svn: 241159
2015-07-01 13:24:28 +00:00
a7a8e9a018
AVX-512: Implemented missing encoding and intrinsics for FMA instructions
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Added tests for DAG lowering ,encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D10796
llvm-svn: 240926
2015-06-29 09:10:00 +00:00
7ec4b7a8bb
[x86][AVX512]
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Add vscalef support
include encoding and intrinsics
review:
http://reviews.llvm.org/D10730
llvm-svn: 240906
2015-06-28 14:30:39 +00:00
6a1a357f1f
AVX-512: Added all SKX forms of GATHER instructions.
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Added intrinsics.
Added encoding and tests.
llvm-svn: 240905
2015-06-28 10:53:29 +00:00
5e2f8c4231
AVX-512: Added all forms of VPABS instruction
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Added all intrinsics, tests for encoding, tests for intrinsics.
llvm-svn: 240386
2015-06-23 08:19:46 +00:00
ba5ab328e5
AVX-512: All forms of VCOPMRESS VEXPAND instructions,
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encoding tests.
llvm-svn: 240272
2015-06-22 11:16:30 +00:00
d3057e5e37
AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and VPERMI2W/D/Q/PS/PD.
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Intrinsics and tests for them are comming in the next patch.
llvm-svn: 240003
2015-06-18 08:56:19 +00:00
4f13f3f9b8
reverted 239999 due to test failures
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llvm-svn: 240001
2015-06-18 08:06:49 +00:00
975a637cd9
AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD
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and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.
llvm-svn: 239999
2015-06-18 07:29:40 +00:00
abe4a79b75
AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
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Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D10430
llvm-svn: 239694
2015-06-14 12:44:55 +00:00
00d9f8457b
AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
Differential Revision: http://reviews.llvm.org/D10310
llvm-svn: 239300
2015-06-08 14:03:17 +00:00
8bdcb69413
Test commit
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llvm-svn: 239019
2015-06-04 07:23:38 +00:00
4078c75bd4
AVX-512: added all SKX forms of VPERMW/D/Q instructions.
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Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.
llvm-svn: 239016
2015-06-04 07:07:13 +00:00
402ebb34af
re-apply 238809
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AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991
llvm-svn: 238923
2015-06-03 13:41:48 +00:00
9e38086534
AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL.
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Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238917
2015-06-03 10:56:40 +00:00
3425c932da
AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
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Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238811
2015-06-02 08:28:57 +00:00
8d897dd05f
revert 238809
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llvm-svn: 238810
2015-06-02 07:45:19 +00:00
17de10f37e
AVX-512: Implemented GETEXP instruction for KNL and SKX
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Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
llvm-svn: 238809
2015-06-02 07:18:14 +00:00
75ede68793
AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
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including encodings.
llvm-svn: 238729
2015-06-01 07:17:23 +00:00
42c96d9c0a
AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for encoding.
by Igor Breger (igor.breger@intel.com )
llvm-svn: 238728
2015-06-01 06:50:49 +00:00
ad9c396838
AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set
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Added encoding tests.
llvm-svn: 237557
2015-05-18 06:42:57 +00:00
1b2f2f1b37
AVX-512: fixed a bug in encoding of VPSRAQ instrcution,
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added a bunch of encoding tests.
llvm-svn: 237232
2015-05-13 07:35:05 +00:00
0d7e9364d1
AVX-512: Added SKX instructions and intrinsics:
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{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236971
2015-05-11 06:05:05 +00:00
29792e9a80
AVX-512: Added all forms of FP compare instructions for KNL and SKX.
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Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 236714
2015-05-07 11:24:42 +00:00
9ebd877a10
AVX-512: enabled tests for AVX512F set
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llvm-svn: 236416
2015-05-04 11:09:41 +00:00
78c424dfca
[X86] Add assembly parser support for mnemonic aliases for AVX-512 vpcmp instructions.
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llvm-svn: 229287
2015-02-15 07:13:48 +00:00
f02ad93270
[X86] Add assembler predicates for the rest of the AVX512 feature flags. This makes the assembly matching consistent across all AVX512 instructions. Without this we were allowing some AVX512 instructions to be parsed always, but not the foundation instructions.
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llvm-svn: 229280
2015-02-15 04:54:55 +00:00
43860838dc
[X86] Improve parsing support AVX/SSE floating point compare instruction mnemonic aliases. They'll now print with the alias the parser received instead of converting to the explicit immediate form.
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llvm-svn: 229266
2015-02-14 21:54:03 +00:00
cbc5703aeb
[AVX512] Added VPBROADCAST{BWDQ} (Load with Broadcast Integer Data from General Purpose Register) encodings for AVX512-BW/VL subsets
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Added encoding tests.
llvm-svn: 223787
2014-12-09 16:38:41 +00:00
af318f7073
[AVX512] Added VBROADCAST{SS/SD} encoding for VL subset.
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Refactored through AVX512_maskable
llvm-svn: 220908
2014-10-30 14:21:47 +00:00
eb12639375
[AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.
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Refactored through AVX512_maskable
llvm-svn: 220806
2014-10-28 18:15:20 +00:00
3e534c93b9
[AVX-512] Expanded rsqrt/rcp instructions to VL subset.
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Refactored multiclass through AVX512_maskable
llvm-svn: 220783
2014-10-28 16:37:13 +00:00
cf7a4a2660
[AVX512] Add vpermil variable version
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This is implemented via a multiclass that derives from the vperm imm
multiclass.
Fixes <rdar://problem/18426089>
llvm-svn: 220737
2014-10-27 23:08:40 +00:00
832ec5e911
[AVX512] FMA support for the 231 variants
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This is asm/diasm-only support, similar to AVX.
For ISeling the register variant, they are no different from 213 other than
whether the multiplication or the addition operand is destructed.
For ISeling the memory variant, i.e. to fold a load, they are no different
than the 132 variant. The addition operand (op3) in both cases can come from
memory. Again the ony difference is which operand is destructed.
There could be a post-RA pass that would convert a 213 or 132 into a 231.
Part of <rdar://problem/17082571>
llvm-svn: 220540
2014-10-24 00:03:00 +00:00
4285c1f8cc
[AVX512] Add DQ subvector inserts
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In AVX512f we support 64x2 and 32x8 inserts via matching them to 32x4 and 64x4
respectively. These are matched by "Alt" Pat<>'s (Alt stands for alternative
VTs).
Since DQ has native support for these intructions, I peeled off the non-"Alt"
part of the baseclass into vinsert_for_size_no_alt. The DQ instructions are
derived from this multiclass. The "Alt" Pat<>'s are disabled with DQ.
Fixes <rdar://problem/18426089>
llvm-svn: 219874
2014-10-15 23:42:17 +00:00
2b5cdbb3de
[AVX512] Add asm-only support for vextract*x4 masking variants
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These derive from the new asm-only masking definitions.
Unfortunately I wasn't able to find a ISel pattern that we could legally
generate for the masking variants. The problem is that since the destination
is v4* we would need VK4 register classes and v4i1 value types to express the
masking. These are however not legal types/classes in AVX512f but only in VL,
so things get complicated pretty quickly. We can revisit this question later
if we have a more pressing need to express something like this.
So the ISel patterns are empty for the masking instructions and the next patch
will add Pat<>s instead to match the intrinsics calls with instructions.
llvm-svn: 219361
2014-10-08 23:25:33 +00:00
29e3b96734
[SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass.
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Added encoding tests
llvm-svn: 216532
2014-08-27 09:34:37 +00:00
2ea081d4d1
[SKX] avx512_icmp_packed multiclass extension
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Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions
Differential Revision: http://reviews.llvm.org/D5024
llvm-svn: 216383
2014-08-25 14:49:34 +00:00
ed8829703f
[SKX] Extended non-temporal load/store instructions for AVX512VL subsets.
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Added avx512_movnt_vl multiclass for handling 256/128-bit forms of instruction.
Added encoding and lowering tests.
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 215536
2014-08-13 10:46:00 +00:00
5ec912881f
[X86] Fixes commit r214890 to match the posted patch
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This was another fallout from my local rebase where something went wrong :(
llvm-svn: 214951
2014-08-06 07:13:12 +00:00
fd2161b710
[AVX512] Add masking variant and intrinsics for valignd/q
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This is similar to what I did with the two-source permutation recently. (It's
almost too similar so that we should consider generating the masking variants
with some tablegen help.)
Both encoding and intrinsic tests are added as well. For the latter, this is
what the IR that the intrinsic test on the clang side generates.
Part of <rdar://problem/17688758>
llvm-svn: 214890
2014-08-05 17:23:04 +00:00
7ca7df0bf9
[SKX] Enabling load/store instructions: encoding
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Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214719
2014-08-04 14:35:15 +00:00
595683da00
[SKX] Enabling mask logic instructions: encoding, lowering
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Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>
llvm-svn: 214081
2014-07-28 13:46:45 +00:00
7a96f01ca1
[SKX] Fix lowercase "error:" in rev 213757
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llvm-svn: 213774
2014-07-23 17:42:13 +00:00
Igor Breger