463f26b4be
Eliminate the other half of the BRCOND optimization, and update
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as many tests as possible.
llvm-svn: 106749
2010-06-24 15:24:03 +00:00
40503396da
Eliminate more uses of llvm-as and llvm-dis.
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llvm-svn: 81290
2009-09-08 23:54:48 +00:00
357645efad
Changed my mind. We now allow remat of instructions whose defs have subreg indices.
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llvm-svn: 76100
2009-07-16 20:15:00 +00:00
84517443ca
Let callers decide the sub-register index on the def operand of rematerialized instructions.
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Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.
llvm-svn: 75900
2009-07-16 09:20:10 +00:00
a5b9645c4b
Split the Add, Sub, and Mul instruction opcodes into separate
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integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.
For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.
This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt
llvm-svn: 72897
2009-06-04 22:49:04 +00:00
a3771d5bd9
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
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llvm-svn: 55564
2008-08-30 09:09:33 +00:00
04cf2e4540
Revert r55467; it causes regressions in UnitTests/Vector/divides,
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Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
2008-08-28 17:22:54 +00:00
6975602024
If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.
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llvm-svn: 55467
2008-08-28 07:53:51 +00:00
e414681352
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
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llvm-svn: 55300
2008-08-25 04:11:42 +00:00
Dan Gohman