5 Commits

Author	SHA1	Message	Date
Matthias Springer	fe0bf7d469	[mlir][vector][NFC] Use CombiningKindAttr instead of StringAttr ... This makes the op consistent with other ops in vector dialect. Differential Revision: https://reviews.llvm.org/D119343	2022-02-10 19:13:29 +09:00
River Riddle	dec8af701f	[mlir] Move SelectOp from Standard to Arithmetic ... This is part of splitting up the standard dialect. See https://llvm.discourse.group/t/standard-dialect-the-final-chapter/ for discussion. Differential Revision: https://reviews.llvm.org/D118648	2022-02-02 14:45:12 -08:00
Alexander Belyaev	57470abc41	[mlir] Move memref.[tensor_load|buffer_cast|clone] to "bufferization" dialect. ... https://llvm.discourse.group/t/rfc-dialect-for-bufferization-related-ops/4712 Differential Revision: https://reviews.llvm.org/D114552	2021-11-25 11:50:39 +01:00
Mogball	7c5ecc8b7e	[mlir][vector] Insert/extract element can accept index ... `vector::InsertElementOp` and `vector::ExtractElementOp` have had their `position` operand changed to accept `AnySignlessIntegerOrIndex` for better operability with operations that use `index`, such as affine loops. LLVM's `extractelement` and `insertelement` can also accept `i64`, so lowering directly to these operations without explicitly inserting casts is allowed. SPIRV's equivalent ops can also accept `i64`. Reviewed By: nicolasvasilache, jpienaar Differential Revision: https://reviews.llvm.org/D114139	2021-11-18 22:40:29 +00:00
Aart Bik	2f0ee17017	[mlir][sparse] test for SIMD reduction chaining in consecutive vector loops ... Reviewed By: bixia Differential Revision: https://reviews.llvm.org/D113197	2021-11-05 10:14:17 -07:00