8a2ae8b766
Only compute intrinsic valuetypes when in a target .td file.
...
llvm-svn: 27197
2006-03-28 00:15:00 +00:00
ac2512a261
revert this, it breaks things.
...
llvm-svn: 27196
2006-03-28 00:03:08 +00:00
c92f688ef3
Add support for decoding iPTR to the right pointer type.
...
llvm-svn: 27188
2006-03-27 22:48:18 +00:00
5386598187
Print error messages like this:
...
tblgen: In STVEBX: Intrinsic 'llvm.ppc.altivec.stvebx' expects 3 operands, not 2 operands!
instead of like this:
tblgen: In STVEBX: Intrinsic 'intrinsic_void expects 3 operands, not 2 operands!
llvm-svn: 27185
2006-03-27 22:21:18 +00:00
8c46ff2d12
Add a missing check which cause an invalid .td file to crash tblgen
...
llvm-svn: 27126
2006-03-25 22:12:44 +00:00
23555e3947
When failing selection for an intrinsic, print this:
...
Cannot yet select: intrinsic %llvm.ppc.altivec.lvx
instead of this:
Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540
llvm-svn: 27110
2006-03-25 06:47:53 +00:00
c8565ed651
Change approach so that we get codegen for free for intrinsics. With this,
...
intrinsics that don't take pointer arguments now work. For example, we can
compile this:
int test3( __m128d *A) {
return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
return _mm_movemask_ps(*A);
}
to this:
_test3:
movl 4(%esp), %eax
movapd (%eax), %xmm0
movmskpd %xmm0, %eax
ret
_test4:
movl 4(%esp), %eax
movaps (%eax), %xmm0
movmskps %xmm0, %eax
ret
llvm-svn: 27090
2006-03-24 23:10:39 +00:00
85586baee7
fix 80 column violations
...
llvm-svn: 27084
2006-03-24 21:52:20 +00:00
e352e7aa85
Parse intrinsics correctly and perform type propagation. This doesn't currently
...
emit the code to select intrinsics, but that is next :)
llvm-svn: 27082
2006-03-24 21:48:51 +00:00
f0729b4067
Add dwarf register numbering to register data.
...
llvm-svn: 27081
2006-03-24 21:15:58 +00:00
bbba823706
Make sure to initialize the TheDef field!
...
llvm-svn: 27078
2006-03-24 20:25:01 +00:00
2c58141fd9
Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
...
the CodeGen* implementations.
Parse the MVT::ValueType for each operand of the intrinsics.
llvm-svn: 27075
2006-03-24 19:49:31 +00:00
97b0d99651
extract some more information from the intrinsic table
...
llvm-svn: 27022
2006-03-24 01:13:55 +00:00
1e0552f838
Add new generated files to be ignored.
...
llvm-svn: 27011
2006-03-23 23:45:32 +00:00
eb0ce0c547
Allow result node to be a simple leaf node. This enable bitconvert patterns
...
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
llvm-svn: 26968
2006-03-23 02:35:32 +00:00
c0af9c6478
Don't forget to promote xform function to an explicit node for def : Pat<>
...
patterns.
llvm-svn: 26929
2006-03-21 20:44:17 +00:00
02ad00ad93
minor code simplification
...
llvm-svn: 26918
2006-03-21 06:42:58 +00:00
af7de1fba8
The node wrapped in PatLeaf<> should be treated as a leaf even if it isn't
...
one, i.e. don't select it.
llvm-svn: 26909
2006-03-20 22:53:06 +00:00
5ece6fa3e0
It should be ok for a xform output type to be different from input type.
...
llvm-svn: 26899
2006-03-20 08:09:17 +00:00
a84bdebfd2
Copy matching pattern's output type info to instruction result pattern.
...
The instruction patterns do not contain enough information to resolve the
exact type of the destination if it of a generic vector type.
llvm-svn: 26892
2006-03-20 06:04:09 +00:00
c1b31d8a83
Add a new SDTCisIntVectorOfSameSize type constraint
...
llvm-svn: 26890
2006-03-20 05:39:48 +00:00
f9d75843f3
getEnumName() missed v8i8, v4i16, and v2i32 types
...
llvm-svn: 26869
2006-03-19 07:57:34 +00:00
f878f6aa54
Fix miscodegen of V_SET0 in PPC.
...
llvm-svn: 26836
2006-03-18 00:40:36 +00:00
09ffafcf54
allow the GCCBuiltinName field to be optional
...
llvm-svn: 26784
2006-03-15 19:15:26 +00:00
c4e2468251
Fix VC++ build error.
...
llvm-svn: 26773
2006-03-15 02:51:05 +00:00
1c32e04b5f
remove typo
...
llvm-svn: 26772
2006-03-15 02:05:38 +00:00
da1a4cc6a4
Autogenerate a table of intrinsic names, so we can map from intrinsic ID to
...
LLVM intrinsic function name.
llvm-svn: 26771
2006-03-15 01:55:21 +00:00
402a573764
Autogenerate code to map from GCC builtin to LLVM intrinsic.
...
llvm-svn: 26770
2006-03-15 01:33:26 +00:00
3eb12e9a2a
Add a newline at the end to avoid gcc warnings.
...
llvm-svn: 26749
2006-03-14 05:59:52 +00:00
fea17a9901
emit a mapping from LLVM intrinsic -> GCC builtins.
...
llvm-svn: 26736
2006-03-13 23:08:44 +00:00
5b6ec4a5ea
Verify that packed type operands have the right size and base type.
...
llvm-svn: 26735
2006-03-13 22:38:57 +00:00
69035f00e3
fix pasto in generate assertion msg
...
llvm-svn: 26706
2006-03-11 00:20:47 +00:00
e3c2db3955
generate side-effect info
...
llvm-svn: 26672
2006-03-09 22:37:52 +00:00
06c7300bf1
Parse mod/ref properties, autogen mod/ref information
...
llvm-svn: 26669
2006-03-09 22:30:49 +00:00
6efe863a70
parse intrinsic types
...
autogenerate an intrinsic verifier
llvm-svn: 26666
2006-03-09 22:05:04 +00:00
6d8104efd2
autogenerate the function name recognizer
...
llvm-svn: 26663
2006-03-09 20:34:19 +00:00
c47620b5d8
Temporary hack to enable more (store (op (load ...))) folding. This makes
...
it possible when a TokenFactor is between the load and store. But is still
missing some cases due to ordering issue.
llvm-svn: 26638
2006-03-09 08:19:11 +00:00
0fab08eae3
Don't generate silly matching code like this:
...
if (N1.getOpcode() == ISD::ADD &&
...)
if (... &&
(N1.getNumOperands() == 1 || !isNonImmUse(N1.Val, N10.Val))) &&
...)
TableGen knows N1 must have more than one operand.
llvm-svn: 26592
2006-03-07 08:31:27 +00:00
ae0f1512c9
Silence a warning.
...
llvm-svn: 26508
2006-03-03 19:34:28 +00:00
f6e846eee8
Fix pasteo
...
llvm-svn: 26499
2006-03-03 06:13:41 +00:00
94f300d15c
remove a bunch of long-dead testing code
...
llvm-svn: 26497
2006-03-03 02:34:28 +00:00
c313d0b712
initial implementation of intrinsic parsing
...
llvm-svn: 26495
2006-03-03 02:32:46 +00:00
73fbe145fd
remove out of date comment
...
llvm-svn: 26492
2006-03-03 02:04:07 +00:00
1edf15e48e
Add support for "-Ifoo" in addition to "-I foo"
...
llvm-svn: 26487
2006-03-03 01:53:40 +00:00
d7f6b55afa
Regenerate
...
llvm-svn: 26486
2006-03-03 01:47:37 +00:00
e7b74c5da1
add support for multiple include directories
...
llvm-svn: 26485
2006-03-03 01:47:14 +00:00
53a2d60bca
New vector type v2f32.
...
llvm-svn: 26437
2006-03-01 01:10:52 +00:00
dc445eadc0
Select inline asm memory operands.
...
llvm-svn: 26349
2006-02-24 02:13:31 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
0add83e969
Fix bugs identified by VC++.
...
llvm-svn: 26287
2006-02-18 03:20:33 +00:00
33f4156663
Bump up pattern cost if the resulting instruction is marked
...
usesCustomDAGSchedInserter.
llvm-svn: 26282
2006-02-18 02:33:09 +00:00
3e15eac81b
Check the new form for bison output into CVS
...
llvm-svn: 26208
2006-02-15 07:24:01 +00:00
ecd162d5cd
Adjust to new form of handling lexer dependencies, this way shouldn't have
...
the problems the old way did.
llvm-svn: 26161
2006-02-14 05:13:13 +00:00
5940bc210e
Call InsertISelMapEntry rather than map insertion operator to prevent overly
...
aggrssive inlining. This reduces Select_store frame size from 24k to 10k.
llvm-svn: 26095
2006-02-09 22:12:27 +00:00
9ce762d51f
Match getTargetNode() changes (now returns SDNode* instead of SDOperand).
...
llvm-svn: 26084
2006-02-09 07:16:09 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
1630c2848f
Hoist all SDOperand declarations within a Select_{opcode}() to the top level
...
to reduce stack memory usage. This is intended to work around the gcc bug.
llvm-svn: 26026
2006-02-07 00:37:41 +00:00
5c76b499aa
Add support for modifier strings in machine instr descriptions. This allows
...
us to avoid creating lots of "Operand" types with different printers, instead
we can fold several together and use modifiers. For example, we can now use:
${target:call} to say that the operand should be printed like a 'call' operand.
llvm-svn: 26024
2006-02-06 23:40:48 +00:00
033e32e5d9
Simplify the variant handling code, no functionality change.
...
llvm-svn: 26023
2006-02-06 22:43:28 +00:00
ebf05bea1b
At the end of isel, select a replacement node for each handle that does not
...
have one. This can happen if a load's real uses are dead (i.e. they do not
have uses themselves).
llvm-svn: 26014
2006-02-06 08:12:55 +00:00
308d0090e6
Name change.
...
llvm-svn: 26013
2006-02-06 06:03:35 +00:00
aa26555b25
Handle HANDLENODE: just return itself.
...
llvm-svn: 26011
2006-02-05 08:46:14 +00:00
368f20e53d
Allow more loads to be folded which were previously prevented from happening
...
due to ordering issue. i.e. they were selected for chain use first.
Now at load select time, check if it is being selected for a chain use and if
it has only a single real use. If so, return a HANDLENODE (with the load as
its operand) in its place and record it.
When it is folded or the load is selected for a real use, the isel records it
as the replacement for the HANDLENODE. The replacement is done when all nodes
are selected.
This scheme exposed a couple of problems where cycles can happen. (See comments
in EmitMatchCode() for descriptions of the problems and their workaround /
solutions.) These problems have been resolved with a small compile time
penality.
llvm-svn: 25995
2006-02-05 06:43:12 +00:00
7ab4579c68
Re-committing the last bit of change. It shouldn't break PPC this time.
...
llvm-svn: 25982
2006-02-05 05:22:18 +00:00
586b06281c
Temporarily revert the last change, which breaks PPC and other targets that
...
DO select things.
llvm-svn: 25970
2006-02-04 09:23:06 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
...
Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
2bcfc52af6
node predicates add to the complexity of a pattern. This ensures that the
...
X86 backend attempts to match small-immediate versions of instructions before
the full size immediate versions.
llvm-svn: 25937
2006-02-03 18:06:02 +00:00
717db484a5
(store (op (load ...))) folding problem. In the generated matching code,
...
Chain is initially set to the chain operand of store node, when it reaches
load, if it matches the load then Chain is set to the chain operand of the
load.
However, if the matching code that follows this fails, isel moves on to the
next pattern but it does not restore Chain to the chain operand of the store.
So when it tries to match the next store / op / load pattern it would fail on
the Chain == load.getOperand(0) test.
The solution is for each chain operand to get a unique name. e.g. Chain10.
llvm-svn: 25931
2006-02-03 06:22:41 +00:00
244e800c19
add a note, ya knoe
...
llvm-svn: 25880
2006-02-01 19:12:23 +00:00
88e616d803
If a pattern's root node is a constant, its size should be 3 rather than 2.
...
llvm-svn: 25870
2006-02-01 06:06:31 +00:00
0d3ef40656
implement test/Regression/TableGen/DagIntSubst.ll
...
llvm-svn: 25836
2006-01-31 06:02:35 +00:00
a8821624d4
simplify some code
...
llvm-svn: 25791
2006-01-29 20:01:35 +00:00
1af077c0c7
it is nice not to chop off bits for those blessed with lots of bits
...
llvm-svn: 25766
2006-01-29 05:22:37 +00:00
49f323a90e
make the casts actually cast to the variable type
...
llvm-svn: 25765
2006-01-29 05:17:22 +00:00
c438c51e82
start of the 64bit safety cleanup
...
llvm-svn: 25764
2006-01-29 05:07:04 +00:00
0e352963fd
Emit series of conditionals with &&, emitting stuff like this:
...
if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() &&
!CodeGenMap.count(N1.getValue(0)) &&
!CodeGenMap.count(N1.getValue(1))) {
instead of this:
if (N1.getOpcode() == ISD::LOAD) {
if (N1.hasOneUse()) {
if (!CodeGenMap.count(N1.getValue(0))) {
if (!CodeGenMap.count(N1.getValue(1))) {
llvm-svn: 25763
2006-01-29 04:41:05 +00:00
7c0149d1d6
Factor matching code that is common between patterns. This works around
...
GCC not jump-threading across this common code, and produces far nicer
output.
llvm-svn: 25762
2006-01-29 04:25:26 +00:00
d3a63de91e
Split out code generation from analysis from emission
...
llvm-svn: 25759
2006-01-29 02:57:39 +00:00
afe9baeb69
move some code around, no change in the generated code
...
llvm-svn: 25758
2006-01-29 02:43:35 +00:00
5255c6c627
now that we have control over emission of the code, emit the code using nested
...
"if" statements (indenting it appropriately, of course) instead of using goto's.
This inverts the logic for all of the if statements, which makes things simpler
to understand in addition to making the generated code easier to read.
llvm-svn: 25757
2006-01-28 20:43:52 +00:00
4c4da201bf
Change PatternCodeEmitter to emit code into a buffer instead of emitting it
...
directly to the output file. This makes things simple because the code doesn't
have to worry about indentation or the case when there is no goto. It also
allows us to indent the code better without touching everything :)
llvm-svn: 25756
2006-01-28 20:31:24 +00:00
a7d6bbff00
Fit to 80 columns, no functionality change
...
llvm-svn: 25752
2006-01-28 19:06:51 +00:00
e251e92c23
Teach tablegen to generate code that is VC++ warning-free.
...
llvm-svn: 25709
2006-01-27 22:22:28 +00:00
e555a92c8d
(store (op (load ...)), ...)
...
If store's chain operand is load, then use load's chain operand instead. If
it isn't (likely a TokenFactor), then do not allow the folding.
llvm-svn: 25708
2006-01-27 22:13:45 +00:00
d98701c639
Subtarget feature can now set any variable to any value
...
llvm-svn: 25678
2006-01-27 08:09:42 +00:00
4d5a93ed28
Use printInlineAsm to, well, print inline asm's.
...
llvm-svn: 25677
2006-01-27 02:10:50 +00:00
543fe4b6aa
PHI and INLINEASM are now builtin instructions provided by Target.td
...
llvm-svn: 25673
2006-01-27 01:45:06 +00:00
db2a5f09f1
If we want to emit things in enum order, use getInstructionsByEnumValue to
...
get the order, don't compute it ourselves.
Don't emit stuff like (14<<0), emit 14 instead.
Don't attempt to get target properties for builtin instructions.
llvm-svn: 25672
2006-01-27 01:44:09 +00:00
ac8b13b32b
There is at least a 'noitinerary' itinerary now
...
llvm-svn: 25671
2006-01-27 01:41:55 +00:00
ec249a3d30
Don't emit JIT code for these instructions
...
llvm-svn: 25669
2006-01-27 01:39:38 +00:00
5815669251
Teach the dag selectors to select InlineAsm nodes.
...
Aren't we happy the pattern selectors are almost all gone?
llvm-svn: 25666
2006-01-26 23:08:55 +00:00
e9025f1f3b
Another folding problem: if a node r/w chain or flag, don't fold it if it
...
has already been selected. The number of use check is not strong enough since
a node can be replaced with newly created target node. e.g. If the original
node has two uses, when it is selected for one of the uses it is replaced with
another. Each node now has a single use but isel still should not fold it.
llvm-svn: 25651
2006-01-26 19:13:45 +00:00
dc8365d4f3
Add a FIXME comment.
...
llvm-svn: 25635
2006-01-26 02:13:31 +00:00
ecfaa0a1c9
Incoming (and optional) flag bugs. They may be embedded inside a inner node of
...
a pattern. Also, nodes which take incoming flag should not be folded if it has
more than one use.
llvm-svn: 25627
2006-01-26 00:22:25 +00:00
c5c228fa59
Fix an optional in flag bug.
...
llvm-svn: 25590
2006-01-24 20:46:50 +00:00
295e196558
Optional InFlag was not being included in node.
...
llvm-svn: 25588
2006-01-24 20:07:38 +00:00
e272b4ec17
Prevent folding of a node with multiple uses if the node already folds a load!
...
Here is an example where the load ended up being done twice:
%A = global uint 0
uint %test(uint %B, ubyte %C) {
%tmp = load uint *%A;
%X = shl uint %tmp, ubyte %C
%Cv = sub ubyte 32, %C
%Y = shr uint %B, ubyte %Cv
%Z = or uint %Y, %X
store uint %Z, uint* %A
ret uint %Z
}
==>
subl $4, %esp
movl %ebx, (%esp)
movl 8(%esp), %edx
movl A, %eax
movb 12(%esp), %bl
movb %bl, %cl
shldl %cl, %edx, %eax
movb %bl, %cl
shldl %cl, %edx, A
movl (%esp), %ebx
addl $4, %esp
ret
llvm-svn: 25471
2006-01-20 01:11:03 +00:00
9e7fb7b2fc
Bug fix. Flag operand number may be calculated incorrectly.
...
llvm-svn: 25465
2006-01-19 21:57:10 +00:00
a15731cd50
Use pattern information to determine whether the use expects this
...
instruction to produce a result. e.g MUL8m, the instruction does not
produce a explicit result. However it produces an implicit result in
AL which would be copied to a temp. The root operator of the matching
pattern is a mul so the use would expect it to produce a result.
llvm-svn: 25458
2006-01-19 10:12:58 +00:00
acec02ebf5
Prevent unnecessary CopyToReg when the same HW register appears in two spots
...
in the pattern.
llvm-svn: 25437
2006-01-19 01:55:45 +00:00
Chris Lattner