9500b343db
Make sure to use the result of the pattern to infer the result type of the
...
instruction, and the result type of the instruction to refine the pattern.
This allows us to write things like this:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
as:
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (VR128:$src)>
and fixes a ppc64 issue.
llvm-svn: 28863
2006-06-20 00:18:02 +00:00
4b464768d1
Improve a comment.
...
llvm-svn: 28833
2006-06-16 18:25:06 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
5d038cf802
Allow more use of iPTR in patterns.
...
llvm-svn: 28790
2006-06-15 00:16:37 +00:00
ff7c28dfdd
Added support for variable_ops.
...
llvm-svn: 28788
2006-06-14 22:22:20 +00:00
1ce02e4c49
Fix support for optional input flag.
...
llvm-svn: 28784
2006-06-14 19:27:50 +00:00
632ee8de55
getOperandNum(): error if specified operand number is out of range.
...
llvm-svn: 28775
2006-06-13 21:47:27 +00:00
deafba0325
Wrap to 80 cols
...
llvm-svn: 28743
2006-06-09 23:59:44 +00:00
5cb722f320
Don't build tblgen with -pedantic or -Wno-long-long
...
llvm-svn: 28638
2006-06-01 18:20:23 +00:00
cc8c0233b6
Can't trust NodeDepth when checking for possibility of load folding creating
...
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.
llvm-svn: 28476
2006-05-25 20:16:55 +00:00
07a4e5ceb1
Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set"
...
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).
llvm-svn: 28458
2006-05-25 00:21:44 +00:00
e7549961cf
Don't make zero-sized static arrays
...
llvm-svn: 28448
2006-05-24 17:31:02 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
886e8f35aa
Now that iPTR is a fully resolved type. We end up losing the type check for
...
patterns that look like this:
def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.
llvm-svn: 28389
2006-05-19 07:24:32 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
fe72285033
Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.
...
llvm-svn: 28376
2006-05-18 00:08:46 +00:00
318a68e1ee
Typo
...
llvm-svn: 28366
2006-05-17 20:55:51 +00:00
f5ef47fe74
Remove PointerType from target definition. Use abstract type MVT::iPTR to
...
represent pointer type.
llvm-svn: 28363
2006-05-17 20:37:59 +00:00
d985d66781
Allow patterns to refer to physical registers that belong to multiple
...
register classes.
llvm-svn: 28323
2006-05-16 07:05:30 +00:00
21c7c23d7e
Noop instruction
...
llvm-svn: 28241
2006-05-12 07:47:00 +00:00
e2c1aedc23
Unused instruction
...
llvm-svn: 28240
2006-05-12 07:42:01 +00:00
229a6d0026
Also add super- register classes info.
...
llvm-svn: 28221
2006-05-11 07:30:26 +00:00
32982836b6
Watch out for the following case:
...
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.
llvm-svn: 28209
2006-05-10 02:47:57 +00:00
d2b8067748
Fix a load folding bug. It is exposed by a multi- resulting instructions
...
def : Pat<> pattern.
llvm-svn: 28208
2006-05-10 00:05:46 +00:00
5e7ba0b049
Add sub-register class information.
...
llvm-svn: 28195
2006-05-09 06:34:26 +00:00
386fb9b0fd
Set isStore of instructions with ISD::TRUNCSTORE root node.
...
llvm-svn: 28075
2006-05-03 02:08:34 +00:00
4b177f089e
Put instruction names into the first non TargetInstrInfo namespace found.
...
llvm-svn: 28043
2006-05-01 23:46:16 +00:00
017b93dd7c
instructions can be in different namespaces. Make sure to use the right
...
one for each instruction.
llvm-svn: 28038
2006-05-01 17:01:17 +00:00
8e63393bc3
Formating
...
llvm-svn: 28036
2006-05-01 09:30:17 +00:00
c2ef5e34a8
Mark instructions whose pattern is (store ...) isStore.
...
llvm-svn: 28032
2006-05-01 09:04:20 +00:00
c5e8ce8b8c
Remove the temporary option: -no-isel-fold-inflight
...
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
54acf6eddc
When isel'ing a node, mark its operands "InFlight" before selecting them. These
...
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.
llvm-svn: 28002
2006-04-28 02:08:10 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
778509c844
Don't fill in fields that no longer exist.
...
llvm-svn: 27898
2006-04-20 18:32:22 +00:00
9235d848b7
Rename AddedCost to AddedComplexity.
...
llvm-svn: 27841
2006-04-19 20:36:09 +00:00
aa3325e925
Allow "let AddedCost = n in" to increase pattern complexity.
...
llvm-svn: 27834
2006-04-19 18:07:24 +00:00
56fdf9ed40
Add missing things to the distribution.
...
llvm-svn: 27650
2006-04-13 06:27:20 +00:00
989b16e488
Fix a typo: Instr* -> Intr*
...
llvm-svn: 27568
2006-04-10 22:02:59 +00:00
726df0bb82
Infer element types for shuffle masks
...
llvm-svn: 27456
2006-04-06 20:36:51 +00:00
09575a9b0a
rename a method, to avoid confusion with llvm intrinsics.
...
llvm-svn: 27455
2006-04-06 20:19:52 +00:00
89df307b61
Adjust the Intrinsics.gen interface a little bit
...
llvm-svn: 27345
2006-04-02 03:35:30 +00:00
470d0181e9
regenerate
...
llvm-svn: 27313
2006-03-31 21:54:11 +00:00
51ffbf18f0
Generalize the previous binary operator support and add a string concatenation
...
operation. This implements Regression/TableGen/strconcat.td.
llvm-svn: 27312
2006-03-31 21:53:49 +00:00
6b7ccbe4d8
Allow bits init values to be used in patterns, turn them into ints.
...
llvm-svn: 27286
2006-03-31 05:25:56 +00:00
03dfc41ba2
Final bugfix for PR724. GCC won't inline varargs functions, so use one to
...
validate the prototype of intrinsic functions. This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.
llvm-svn: 27283
2006-03-31 04:48:26 +00:00
3abe174165
When emitting code for the verifier, instead of emitting each case statement
...
independently, batch up checks so that identically typed intrinsics share
verifier code. This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.
llvm-svn: 27281
2006-03-31 04:24:58 +00:00
bab91842ba
regenerate
...
llvm-svn: 27264
2006-03-30 22:51:12 +00:00
b59cf3cff4
Implement Regression/TableGen/DagDefSubst.ll
...
llvm-svn: 27263
2006-03-30 22:50:40 +00:00
c2c8b58cf6
Don't sort the names before outputing the intrinsic name table. It causes a
...
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)
llvm-svn: 27237
2006-03-28 22:25:56 +00:00
7c9740a9ed
Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums.
...
Also, don't emit dynamic checks when we can compute them statically
llvm-svn: 27202
2006-03-28 00:41:33 +00:00
Chris Lattner