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Author SHA1 Message Date
Robert Khasanov 595683da00 [SKX] Enabling mask logic instructions: encoding, lowering 
Instructions: KAND{BWDQ}, KANDN{BWDQ}, KOR{BWDQ}, KXOR{BWDQ}, KXNOR{BWDQ}

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 214081
 2014-07-28 13:46:45 +00:00
Robert Khasanov 74acbb7767 [SKX] Enabling mask instructions: encoding, lowering 
KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 213757
 2014-07-23 14:49:42 +00:00
Elena Demikhovsky f164859efc AVX-512: Fixed intrinsic of VSQRTPS/PD instructions. 
I set number and types of parameters according to GCC intrinsics.

llvm-svn: 213640
 2014-07-22 11:07:31 +00:00
Robert Khasanov bfa0131365 [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features. 
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)

Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 213545
 2014-07-21 14:54:21 +00:00
Adam Nemet 79580db918 [X86] AVX512: Only allow k1-k7 as predicates to vpcmp* 
As destination k0 is allowed but not as predicate/writemask.

I also modified the test to allow checking of error messages by the assembler.
I applied a similar approach to the test ret.s in the same directory.

llvm-svn: 212504
 2014-07-08 00:22:32 +00:00
Adam Nemet 11dd5cf9f1 [X86] AVX512: Allow writemask argument in vpermt* intrinsics 
llvm-svn: 212223
 2014-07-02 21:26:01 +00:00
Adam Nemet efe9c98a16 [X86] AVX512: Generate Pat<>'s for the vpermt2* intrinsics via multiclass 
This new multiclass, avx512_perm_table_3src derives from the current one and
provides the Pat<>.  The next patch will add another Pat<> that uses the
writemask.

Note that I dropped the type annotation from the intrinsic call, i.e.: (v16f32
VR512:$src1) -> R512:$src1.  I think that this should be fine (at least many
intrinsic calls don't provide them) and it greatly reduces the number of
template arguments.

llvm-svn: 212222
 2014-07-02 21:25:58 +00:00
Adam Nemet 2415a497b5 [X86] AVX512: Add writemask variants for vperm*2* 
This includes assembler and codegen support (see the new tests in
avx512-encodings.s and avx512-shuffle.ll).

<rdar://problem/17492620>

llvm-svn: 212221
 2014-07-02 21:25:54 +00:00
Adam Nemet 16de2486cb [X86] AVX512: Allow writemasks with vpcmp 
For now I only updated the _alt variants.  The main variants are used by
codegen and that will need a bit more work to trigger.

<rdar://problem/17492620>

llvm-svn: 212114
 2014-07-01 18:03:45 +00:00
Adam Nemet 1efcb90fcd [X86] AVX512: Factor generating the AsmString into avx512_icmp_cc 
Adding a writemask variant would require a third asm string to be passed to
the template.  Generate the AsmString in the template instead.

No change in X86.td.expanded.

llvm-svn: 212113
 2014-07-01 18:03:43 +00:00
Adam Nemet 73f72e15ac [X86] AVX512: Add vbroadcasti* 
For now I used a separate template for these sub-vector/tuple broadcasts
rather than sharing the mem variants with avx512_int_broadcast_rm.

<rdar://problem/17402869>

llvm-svn: 211828
 2014-06-27 00:43:38 +00:00
Adam Nemet 905832bf87 [X86] AVX512: Fix asm syntax for packed vcmp 
The *_alt defs for vcmp are used by the InstParser (the asm string in the main
def is used by the InstPrinter) .  The former was accepting vector registers
as destination rather than mask registers.

llvm-svn: 211750
 2014-06-26 00:21:12 +00:00
Adam Nemet efd0785d82 [X86] AVX512: Add non-temporal stores 
Note that I followed the AVX2 convention here and didn't add LLVM intrinsics
for stores.  These can be generated with the nontemporal hint on LLVM IR
stores (see new test). The GCC builtins are lowered directly into nontemporal
stores.

<rdar://problem/17082571>

llvm-svn: 211176
 2014-06-18 16:51:10 +00:00
Adam Nemet ded81a810c [X86] AVX512: Specify compressed displacement for vmovntdqa 
Use the max 64-bit element size with EVEX_CD8.  This should work since element
size is ignored for a full-vector access (FVM).

llvm-svn: 211175
 2014-06-18 16:51:07 +00:00
Cameron McInally f10a7c963b Add pattern for unsigned v4i32->v4f64 convert on AVX512. 
llvm-svn: 211164
 2014-06-18 14:04:37 +00:00
Cameron McInally 0d0489cea6 Hook up vector int_ctlz for AVX512. 
llvm-svn: 211024
 2014-06-16 14:12:28 +00:00
Cameron McInally c43c8f9458 Add HasCDI predicate to AVX512 VPBROADCASTM*. 
llvm-svn: 210892
 2014-06-13 11:40:31 +00:00
Cameron McInally 5d1b7b94e4 Add AVX512 masked leadz instrinsic support. 
llvm-svn: 210652
 2014-06-11 12:54:45 +00:00
Adam Nemet 7f62b23e92 [X86] AVX512: Add vmovntdqa 
Along with the corresponding intrinsic and tests.

llvm-svn: 210543
 2014-06-10 16:39:53 +00:00
Elena Demikhovsky 8e8fde8e93 AVX-512: changes in intrinsics 
1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed.
2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012).
3) I added gather/scatter prefetch intrinsics.
4) I fixed MRMm encoding for masked instructions.

llvm-svn: 208522
 2014-05-12 07:18:51 +00:00
Elena Demikhovsky e73333a50f AVX-512: minor change in rndscale intrinsic 
llvm-svn: 207937
 2014-05-04 13:35:37 +00:00
Elena Demikhovsky 299cf511c4 AVX-512: optimized a shuffle pattern to VINSERTI64x4. 
Added intrinsics for VPERMT2PS/PD/D/Q instructions.

llvm-svn: 207513
 2014-04-29 09:09:15 +00:00
Elena Demikhovsky acc5c9e83e AVX-512: store and truncstore for i1 values 
llvm-svn: 206897
 2014-04-22 14:13:10 +00:00
Robert Khasanov 189e7fdcfb [AVX512] Implemented integer conversions up/down with masking. 
Added encoding tests.

llvm-svn: 206884
 2014-04-22 11:36:19 +00:00
Filipe Cabecinhas 20352216fb Rename X86insrtps to the proper instruction name. 
Summary:
The INSERTPS pattern fragment was called insrtps (mising 'e'), which
would make it harder to grep for the patterns related to this instruction.
Renaming it to use the proper instruction name.

Reviewers: nadav

CC: llvm-commits

Differential Revision: http://reviews.llvm.org/D3443

llvm-svn: 206779
 2014-04-21 20:07:29 +00:00
Elena Demikhovsky cf0b9bafc3 AVX-512: insert element to mask vector; store i1 data 
Implemented INSERT_VECTOR_ELT operation for v16i1 and v8i1 vectors;
Implemented "store" for i1 type

llvm-svn: 205850
 2014-04-09 12:37:50 +00:00
Elena Demikhovsky 3dcfbdfa54 AVX-512: Added fp_to_uint and uint_to_fp patterns. 
llvm-svn: 205754
 2014-04-08 07:24:02 +00:00
Robert Khasanov ed0b2e9733 Test commit. 
llvm-svn: 205214
 2014-03-31 16:01:38 +00:00
Elena Demikhovsky bb2f6b72d3 AVX-512: Implemented masking for integer arithmetic & logic instructions. 
By Robert Khasanov rob.khasanov@gmail.com

llvm-svn: 204906
 2014-03-27 09:45:08 +00:00
Cameron McInally 4532596b8f Fix AVX512 Gather and Scatter execution domains. 
llvm-svn: 204804
 2014-03-26 13:50:50 +00:00
Elena Demikhovsky fd05667276 AVX-512: masked load/store + intrinsics for them. 
llvm-svn: 203790
 2014-03-13 12:05:52 +00:00
Elena Demikhovsky f7c1b16591 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them. 
By Robert Khazanov.

llvm-svn: 203098
 2014-03-06 08:45:30 +00:00
Elena Demikhovsky 9737e3886b AVX-512: Fixed extract_vector_elt for v8i1 vector 
llvm-svn: 202624
 2014-03-02 09:19:44 +00:00
Elena Demikhovsky a5c38cbb45 AVX-512: Fixed encoding of VPCMPEQ and VPCMPGT 
llvm-svn: 202015
 2014-02-24 10:08:30 +00:00
Elena Demikhovsky 3ebfe11532 AVX-512: Fixed encoding of VPTESTMQ 
llvm-svn: 201980
 2014-02-23 14:28:35 +00:00
Elena Demikhovsky c96570172a AVX-512: Assembly parsing of broadcast semantic in AVX-512; imlemented by Nis Zinovy (zinovy.y.nis@intel.com) 
Fixed truncate i32 to i1; a test will be provided in the next commit.

llvm-svn: 201757
 2014-02-20 06:34:39 +00:00
Cameron McInally 7b544f0297 Fix AVX512 vector sqrt assembly strings. 
llvm-svn: 201681
 2014-02-19 15:16:09 +00:00
Craig Topper 5ccb61781f Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. 
llvm-svn: 201538
 2014-02-18 00:21:49 +00:00
Elena Demikhovsky 750498c77b AVX-512: implemented zext fron i1 to i16 
llvm-svn: 201502
 2014-02-17 07:29:33 +00:00
Elena Demikhovsky 1fad075974 AVX-512: simpyfied BUILD_VECTOR for masks; fixed cmp/test sequence 
llvm-svn: 201487
 2014-02-16 11:34:23 +00:00
Elena Demikhovsky 2aafc22ed9 AVX-512: Optimized BUILD_VECTOR pattern; 
fixed encoding of VEXTRACTPS instruction.

llvm-svn: 201134
 2014-02-11 07:25:59 +00:00
Elena Demikhovsky 9f423d6f25 AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors. 
llvm-svn: 201066
 2014-02-10 07:02:39 +00:00
Elena Demikhovsky a30e437659 AVX-512: Added intrinsic for cvtph2ps. 
Added VPTESTNM instruction.
Added a pattern to vselect (lit tests will follow).

llvm-svn: 200823
 2014-02-05 07:05:03 +00:00
Craig Topper da7160d6d2 Simplify some x86 format classes and remove some ambiguities in their application. 
llvm-svn: 200608
 2014-02-01 08:17:56 +00:00
Craig Topper fb1746beec Remove duplicate pattern and add predicate checks on other patterns. 
llvm-svn: 200455
 2014-01-30 06:03:19 +00:00
Elena Demikhovsky a5d38a39a0 AVX-512: added VPERM2D VPERM2Q VPERM2PS VPERM2PD instructions, 
they give better sequences than VPERMI

llvm-svn: 199893
 2014-01-23 14:27:26 +00:00
Elena Demikhovsky 767fc967b4 AVX-512: optimized scalar compare patterns 
removed AVX512SI format, since it is similar to AVX512BI.

llvm-svn: 199217
 2014-01-14 15:10:08 +00:00
Craig Topper ae11aed9d7 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
Elena Demikhovsky b19c9dc1a1 AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

llvm-svn: 199102
 2014-01-13 12:55:03 +00:00
Elena Demikhovsky 172a27c750 AVX-512: Added more intrinsics for pmin/pmax, pabs, blend, pmuldq. 
llvm-svn: 198745
 2014-01-08 10:54:22 +00:00
Elena Demikhovsky 3629b4aa0e AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without) 
llvm-svn: 198593
 2014-01-06 08:45:54 +00:00
Elena Demikhovsky f404e054a1 AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD; 
Optimized a truncate pattern.

llvm-svn: 198562
 2014-01-05 14:21:07 +00:00
Elena Demikhovsky 52e4a0e109 AVX-512: Added more intrinsics for convert and min/max. 
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557
 2014-01-05 10:46:09 +00:00
Craig Topper 0550ce7ac1 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper 3484fc2161 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper 9dd48c8ed4 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Elena Demikhovsky de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Elena Demikhovsky b64d7e8586 AVX-512: Result type of scalar SETCC is MVT::i1 for AVX-512. 
llvm-svn: 198008
 2013-12-25 10:06:40 +00:00
Elena Demikhovsky 64c9548d66 AVX-512: fixed some patterns for MVT::i1 
llvm-svn: 197981
 2013-12-24 14:24:07 +00:00
Elena Demikhovsky fe24a30e38 AVX512: SETCC returns i1 for AVX-512 and i8 for all others 
llvm-svn: 197876
 2013-12-22 10:13:18 +00:00
Elena Demikhovsky c5f6726a24 AVX-512: Added implementation of CONCAT_VECTORS for v8i1 vectors (by Alexey Bader). 
Added implementation of "truncate" from integer type (i64/i32/i16/i8) to i1.

llvm-svn: 197482
 2013-12-17 08:33:15 +00:00
Elena Demikhovsky 47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky cf08809813 AVX-512: Removed "z" suffix from AVX-512 instructions, since it is incompatible with GCC. 
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll
I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions).

llvm-svn: 197041
 2013-12-11 14:31:04 +00:00
Elena Demikhovsky e382c3fdcd AVX-512: changed intrinsics for mask operations 
llvm-svn: 196918
 2013-12-10 13:53:10 +00:00
Elena Demikhovsky 6270b388c8 AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin form 
llvm-svn: 196914
 2013-12-10 11:58:35 +00:00
Cameron McInally e3cc4aacb9 Update AVX512 vector blend intrinsic names. 
llvm-svn: 196581
 2013-12-06 13:35:35 +00:00
Cameron McInally 30bbb214e5 Add AVX512 patterns for v16i32 broadcast and v2i64 zero extend load. 
Patch by Aleksey Bader.

llvm-svn: 196435
 2013-12-05 00:11:25 +00:00
Cameron McInally cbb51dacfb Fix assembly syntax for AVX512 vector blend instructions. 
llvm-svn: 196393
 2013-12-04 18:05:36 +00:00
Elena Demikhovsky 0a74b7da35 AVX-512: Handled extractelement from mask vector; 
Added VMOSHDUP/VMOVSLDUP shuffle instructions.

llvm-svn: 194691
 2013-11-14 11:29:27 +00:00
Cameron McInally d80f7d34de Add support for AVX512 masked vector blend intrinsics. 
llvm-svn: 194006
 2013-11-04 19:14:56 +00:00
Elena Demikhovsky dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Cameron McInally 394d557f41 Add AVX512 unmasked integer broadcast intrinsics and support. 
llvm-svn: 193748
 2013-10-31 13:56:31 +00:00
Elena Demikhovsky 199c823555 AVX-512: PMIN/PMAX intrinsics and patterns 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193497
 2013-10-27 08:18:37 +00:00
Quentin Colombet 8761a8f5c0 [X86][AVX512] Add patterns that match the AVX512 floating point register vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193422
 2013-10-25 18:04:12 +00:00
Quentin Colombet 4bf1c282c2 [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast intrinsics. 
Patch by Cameron McInally <cameron.mcinally@nyu.edu>

llvm-svn: 193421
 2013-10-25 17:47:18 +00:00
Elena Demikhovsky dd0794e51b AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsics 
llvm-svn: 193312
 2013-10-24 07:16:35 +00:00
Elena Demikhovsky 1f3ed4169c AVX-512: aligned / unaligned load and store for 512-bit integer vectors. 
llvm-svn: 193156
 2013-10-22 09:19:28 +00:00
Lang Hames 2783993fca X86 vector element shift-by-immediate instructions take i8 immediates. Make 
the instruction defenitions and ISEL reflect this.

Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).

Fixes <rdar://problem/14968098>

llvm-svn: 193096
 2013-10-21 17:51:24 +00:00
Craig Topper 88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Elena Demikhovsky a3a714082b AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics. 
llvm-svn: 192283
 2013-10-09 08:16:14 +00:00
Andrew Trick 15a4774345 Add missing HasAVX512 predicate. 
This was only working because AVX had cheaper rules in all cases.
I'm sure there are other places in this file where predicates are missing.

llvm-svn: 192276
 2013-10-09 05:11:10 +00:00
Craig Topper a328ee42cf Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB prefix and keeps the mnemonic from starting with an extra 'v' 
llvm-svn: 192272
 2013-10-09 04:24:38 +00:00
Elena Demikhovsky 2e408aefe0 AVX-512: added scalar convert instructions and intrinsics. 
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
 2013-10-06 13:11:09 +00:00
Elena Demikhovsky 462a2d235b AVX-512: fixed shuffle lowering 
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
 2013-10-06 06:11:18 +00:00
Elena Demikhovsky 85aeffaf5c AVX-512: Fixed encoding of VMOVQ instruction. 
llvm-svn: 191889
 2013-10-03 12:03:26 +00:00
Elena Demikhovsky 34586e7d41 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target 
llvm-svn: 191818
 2013-10-02 12:20:42 +00:00
Elena Demikhovsky b30371cb6b AVX-512: Added TB prefix to all instructions without prefixes, 
otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.

llvm-svn: 191812
 2013-10-02 06:39:07 +00:00
Elena Demikhovsky 3b75f5d282 AVX-512: Added X86vzmovl patterns 
llvm-svn: 191733
 2013-10-01 08:38:02 +00:00
Craig Topper dbe8b7d236 Put HasAVX512 predicate on some patterns to properly disable them when AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. 
llvm-svn: 191490
 2013-09-27 07:20:47 +00:00
Elena Demikhovsky ac3e8eb9f0 AVX-512: Converted to Unix style 
llvm-svn: 190851
 2013-09-17 07:34:34 +00:00
Preston Gurd 3fe264d625 Adds support for Atom Silvermont (SLM) - -march=slm 
Implements Instruction scheduler latencies for Silvermont,
using latencies from the Intel Silvermont Optimization Guide.

Auto detects SLM.

Turns on post RA scheduler when generating code for SLM.

llvm-svn: 190717
 2013-09-13 19:23:28 +00:00
Elena Demikhovsky 8952974e29 AVX-512: implemented extractelement with variable index. 
Added parsing of mask register and "zeroing" semantic, like {%k1} {z}.

llvm-svn: 190595
 2013-09-12 08:55:00 +00:00
Elena Demikhovsky 4def4b088f AVX-512: Added GATHER and SCATTER instructions. 
llvm-svn: 189729
 2013-09-01 14:24:41 +00:00
Elena Demikhovsky 980c6b08b1 AVX-512: added extend and truncate instructions. 
llvm-svn: 189580
 2013-08-29 11:56:53 +00:00
Elena Demikhovsky 9a5ed9c3bd AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABS 
llvm-svn: 189472
 2013-08-28 11:21:58 +00:00
Elena Demikhovsky 93eeb47d49 AVX-512: added conversion instructions. 
llvm-svn: 189349
 2013-08-27 13:54:04 +00:00
Elena Demikhovsky 12f24673e0 AVX-512: Added FMA instructions. 
llvm-svn: 189326
 2013-08-27 08:39:25 +00:00
Elena Demikhovsky 0a2b6290f1 AVX-512: Added shuffle instructions - 
VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN
 single and double forms.

llvm-svn: 189215
 2013-08-26 12:45:35 +00:00
Elena Demikhovsky f8f478b19d AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectors 
llvm-svn: 189189
 2013-08-25 12:54:30 +00:00
Elena Demikhovsky c35219e3ee AVX-512: Added masked SHIFT commands, more encoding tests 
llvm-svn: 189005
 2013-08-22 12:18:28 +00:00
Elena Demikhovsky 33d447a2d6 AVX-512: Added SHIFT instructions. 
llvm-svn: 188899
 2013-08-21 09:36:02 +00:00
Elena Demikhovsky 540d582594 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ 
llvm-svn: 188786
 2013-08-20 11:00:29 +00:00
Elena Demikhovsky 1490c5eb5b AVX-512: added arithmetic and logical operations. 
ADD, SUB, MUL integer and FP types. OR, AND, XOR.
Added embeded broadcast form for these instructions.

llvm-svn: 188673
 2013-08-19 13:26:14 +00:00
Elena Demikhovsky 3ce8dbbac2 AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions. 
llvm-svn: 188637
 2013-08-18 13:08:57 +00:00
Craig Topper 8c929627d9 Don't use v16i32 for load pattern matching. All 512-bit loads are cated to v8i64. 
llvm-svn: 188534
 2013-08-16 06:07:34 +00:00
Elena Demikhovsky 60b1f289f2 AVX-512: Added CMP and BLEND instructions. 
Lowering for SETCC.

llvm-svn: 188265
 2013-08-13 13:24:07 +00:00
Elena Demikhovsky cf5b1458e6 AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions. 
Added a test for shuffles using VPERM.

llvm-svn: 188147
 2013-08-11 07:55:09 +00:00
Elena Demikhovsky 45c54ad8dc AVX-512 set: Added BROADCAST instructions 
with lowering logic and a test.

llvm-svn: 187884
 2013-08-07 12:34:55 +00:00
Elena Demikhovsky 40864b690b AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types. 
Added intrinsics and tests.

llvm-svn: 187717
 2013-08-05 08:52:21 +00:00
Elena Demikhovsky cd46691728 AVX-512 set: added VEXTRACTPS instruction 
llvm-svn: 187705
 2013-08-04 10:46:07 +00:00
Elena Demikhovsky 67b05fc0b3 Added INSERT and EXTRACT intructions from AVX-512 ISA. 
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.

llvm-svn: 187491
 2013-07-31 11:35:14 +00:00