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534 Commits

Author SHA1 Message Date
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Dan Gohman 5f6a9da530 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Evan Cheng aa39b39eec Indexed loads each has 2 outputs. 
llvm-svn: 40658
 2007-08-01 00:12:08 +00:00
Dan Gohman e379f08b19 More explicit keywords. 
llvm-svn: 40589
 2007-07-30 14:51:59 +00:00
Duncan Sands 644f917358 Support for trampolines, except for X86 codegen which is 
still under discussion.

llvm-svn: 40549
 2007-07-27 12:58:54 +00:00
Dan Gohman cf0a5349de Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 9d5df0a5f6 Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng 22b0c344db Only adjust esp around calls in presence of alloca. 
llvm-svn: 40030
 2007-07-19 00:42:58 +00:00
Chris Lattner 396156e00b no email addrs in file headers 
llvm-svn: 39962
 2007-07-17 05:56:43 +00:00
Anton Korobeynikov 383a324735 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Dale Johannesen 85ee72f7ba ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
 2007-07-12 16:45:35 +00:00
Dale Johannesen e59411d056 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).

llvm-svn: 39743
 2007-07-11 18:32:38 +00:00
Evan Cheng 94579dbd2e Didn't mean the last commit. Revert. 
llvm-svn: 38515
 2007-07-10 22:00:16 +00:00
Evan Cheng effa7467b6 Update. 
llvm-svn: 38513
 2007-07-10 21:49:47 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Chris Lattner 517290ae52 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng 881248c4e1 No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng 3650b2c278 Incorrect check. 
llvm-svn: 37962
 2007-07-06 23:23:19 +00:00
Evan Cheng 76a97c5f8a Do away with ImmutablePredicateOperand. 
llvm-svn: 37961
 2007-07-06 23:22:46 +00:00
Evan Cheng 0a42fdf346 Print the s bit if the instruction is toggled to its CPSR setting form. 
llvm-svn: 37932
 2007-07-06 01:01:34 +00:00
Evan Cheng 5c66888580 PredicateDefOperand -> OptionalDefOperand. 
llvm-svn: 37931
 2007-07-06 01:00:49 +00:00
Evan Cheng 9546a5c7de Initial ARM JIT support by Raul Fernandes Herbster. 
llvm-svn: 37926
 2007-07-05 21:15:40 +00:00
Evan Cheng 085314b455 Unbreak the build. 
llvm-svn: 37914
 2007-07-05 17:13:19 +00:00
Gabor Greif e16561cd5d Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Evan Cheng 94f04c6fc9 Reflects the chanegs made to PredicateOperand. 
llvm-svn: 37898
 2007-07-05 07:18:20 +00:00
Evan Cheng a7f77599a4 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37897
 2007-07-05 07:17:13 +00:00
Evan Cheng 7e90b11550 Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
llvm-svn: 37896
 2007-07-05 07:15:27 +00:00
Evan Cheng aa3b8014bd Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng 49ffa1e488 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37894
 2007-07-05 07:11:03 +00:00
John Criswell 2660cef6d7 Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Evan Cheng 335c65e9a4 Silence a warning. 
llvm-svn: 37737
 2007-06-26 18:31:22 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Owen Anderson 0c550df9d2 Fix the build. 
llvm-svn: 37705
 2007-06-22 16:59:54 +00:00
Dan Gohman 309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Dale Johannesen 485531ea9b Quote complex names for Darwin X86 and ARM. 
llvm-svn: 37700
 2007-06-22 00:54:56 +00:00
Evan Cheng 77d61e6f6d Be more conservative of duplicating blocks. 
llvm-svn: 37669
 2007-06-19 23:55:02 +00:00
Evan Cheng c3c949b473 Allow predicated immediate ARM to ARM calls. 
llvm-svn: 37659
 2007-06-19 21:05:09 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng 36b1f5476e Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt. 
llvm-svn: 37606
 2007-06-15 21:15:00 +00:00
Dale Johannesen c68554683d Handle blocks with 2 unconditional branches in AnalyzeBranch. 
llvm-svn: 37571
 2007-06-13 17:59:52 +00:00
Evan Cheng 5514bbef46 Add a utility routine to check for unpredicated terminator instruction. 
llvm-svn: 37528
 2007-06-08 21:59:56 +00:00
Lauro Ramos Venancio c7ebbaa10e Define AsmTransCBE for ARM. 
llvm-svn: 37527
 2007-06-08 21:06:23 +00:00
Evan Cheng 6740da9407 Fix ARM condition code subsumission check. 
llvm-svn: 37517
 2007-06-08 09:14:47 +00:00
Evan Cheng f62a5afb98 tBcc is not a barrier. 
llvm-svn: 37516
 2007-06-08 09:13:23 +00:00
Evan Cheng 842be09d86 Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a compilation warning? I blame it on the FE folks. 
llvm-svn: 37484
 2007-06-07 01:37:54 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng 5c48958a61 Print predicate of the second instruction of the two-piece constant MI. 
llvm-svn: 37437
 2007-06-05 18:55:18 +00:00