fdf10e6197
[RISCV] Use X0 as destination of inserted vsetvli when possible.
...
We aren't going to connect the result to anything so we might
as well avoid allocating a register.
Reviewed By: frasercrmck, HsiangKai
Differential Revision: https://reviews.llvm.org/D102031
2021-05-26 13:08:51 -07:00
6e360460f1
[RISCV] Use v8-v23 as argument registers to conform to the proposal.
...
The maximum LMUL is 8. We need 16 vector registers for two LMUL-8
arguments. The modification follows the proposal of psABI in
https://github.com/riscv/riscv-elf-psabi-doc/pull/171
Differential Revision: https://reviews.llvm.org/D95134
2021-01-22 07:55:24 +08:00
a8b96eadfd
[RISCV] Implement vssseg intrinsics.
...
Define vlsseg intrinsics and pseudo instructions. Lower vlsseg
intrinsics to pseudo instructions in RISCVDAGToDAGISel.
Differential Revision: https://reviews.llvm.org/D94863
2021-01-21 11:51:35 +08:00
Craig Topper