2 Commits

Author	SHA1	Message	Date
Sander de Smalen	a5e0389b2a	[AArch64] Define ACLE FP conversion intrinsics with more specific predicate. ... This patch changes the FP conversion intrinsics to take a predicate that matches the number of lanes for the vector with the widest element type as opposed to using <vscale x 16 x i1>. For example: ```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)``` now uses <vscale x 4 x i1> instead of <vscale x 16 x i1> And similar for: ```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)``` where the predicate now matches the wider type, so <vscale x 2 x i1>. Reviewers: efriedma, SjoerdMeijer, paulwalker-arm, rengolin Reviewed By: efriedma Tags: #clang Differential Revision: https://reviews.llvm.org/D78402	2020-04-23 10:53:23 +01:00
Kerry McLaughlin	4a649ad21a	[AArch64][SVE] Implement floating-point conversion intrinsics ... Summary: Adds intrinsics for the following: - fcvt - fcvtzs & fcvtzu - scvtf & ucvtf - fcvtlt, fcvtnt - fcvtx & fcvtxnt Reviewers: huntergr, sdesmalen, dancgr, mgudim, efriedma Reviewed By: sdesmalen Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cameron.mcinally, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70180	2019-11-26 10:31:47 +00:00