Commit Graph

185972 Commits

Author SHA1 Message Date
Heejin Ahn daeead4b02 [WebAssembly] Fix unwind mismatch stat computation
Summary:
There was a bug when computing the number of unwind destination
mismatches in CFGStackify. When there are many mismatched calls that
share the same (original) destination BB, they have to be counted
separately.

This also fixes a typo and runs `fixUnwindMismatches` only when the wasm
exception handling is enabled. This is to prevent unnecessary
computations and does not change behavior.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68552

llvm-svn: 373975
2019-10-07 22:19:40 +00:00
Heejin Ahn ae5bad7277 [llvm-lipo] Add TextAPI to LINK_COMPONENTS
Summary:
D68319 uses `MachO::getCPUTypeFromArchitecture` and without this builds
with `-DBUILD_SHARED_LIBS=ON` fail.

Reviewers: alexshap

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68594

llvm-svn: 373974
2019-10-07 22:11:30 +00:00
Johannes Doerfert ee33c61e34 [Attributor][FIX] Remove assertion wrong for on invalid IRPositions
llvm-svn: 373972
2019-10-07 21:48:08 +00:00
Cameron McInally 60786f9143 [llvm-c] Add UnaryOperator to LLVM_FOR_EACH_VALUE_SUBCLASS macro
Note that we are not sure where the tests for these functions lives. This was discussed in the Phab Diff.

Differential Revision: https://reviews.llvm.org/D68588

llvm-svn: 373969
2019-10-07 21:33:39 +00:00
Heejin Ahn 58af5be28d [WebAssembly] Add memory intrinsics handling to mayThrow()
Summary:
Previously, `WebAssembly::mayThrow()` assumed all inputs are global
addresses. But when intrinsics, such as `memcpy`, `memmove`, or `memset`
are lowered to external symbols in instruction selection and later
emitted as library calls. And these functions don't throw.

This patch adds handling to those memory intrinsics to `mayThrow`
function. But while most of libcalls don't throw, we can't guarantee all
of them don't throw, so currently we conservatively return true for all
other external symbols.

I think a better way to solve this problem is to embed 'nounwind' info
in `TargetLowering::CallLoweringInfo`, so that we can access the info
from the backend. This will also enable transferring 'nounwind'
properties of LLVM IR instructions. Currently we don't transfer that
info and we can only access properties of callee functions, if the
callees are within the module. Other targets don't need this info in the
backend because they do all the processing before isel, but it will help
us because that info will reduce code size increase in fixing unwind
destination mismatches in CFGStackify.

But for now we return false for these memory intrinsics and true for all
other libcalls conservatively.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68553

llvm-svn: 373967
2019-10-07 21:14:45 +00:00
Alexander Shaposhnikov f5d700ac05 [llvm-lipo] Relax the check of the specified input file architecture
cctools lipo only compares the cputypes when it verifies that
the specified (via -arch) input file and the architecture match.
This diff adjusts the behavior of llvm-lipo accordingly. 

Differential revision: https://reviews.llvm.org/D68319

Test plan: make check-all

llvm-svn: 373966
2019-10-07 21:14:22 +00:00
Johannes Doerfert 1097fab1cf [Attributor] Deduce memory behavior of functions and arguments
Deduce the memory behavior, aka "read-none", "read-only", or
"write-only", for functions and arguments.

Reviewers: sstefan1, uenoku

Subscribers: hiraditya, bollu, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67384

llvm-svn: 373965
2019-10-07 21:07:57 +00:00
Roman Lebedev 7cdeac43e5 [InstCombine] Fold conditional sign-extend of high-bit-extract into high-bit-extract-with-signext (PR42389)
This can come up in Bit Stream abstractions.

The pattern looks big/scary, but it can't be simplified any further.
It only is so simple because a number of my preparatory folds had
happened already (shift amount reassociation / shift amount
reassociation in bit test, sign bit test detection).

Highlights:
* There are two main flavors: https://rise4fun.com/Alive/zWi
  The difference is add vs. sub, and left-shift of -1 vs. 1
* Since we only change the shift opcode,
  we can preserve the exact-ness: https://rise4fun.com/Alive/4u4
* There can be truncation after high-bit-extraction:
  https://rise4fun.com/Alive/slHc1   (the main pattern i'm after!)
  Which means that we need to ignore zext of shift amounts and of NBits.
* The sign-extending magic can be extended itself (in add pattern
  via sext, in sub pattern via zext. not the other way around!)
  https://rise4fun.com/Alive/NhG
  (or those sext/zext can be sinked into `select`!)
  Which again means we should pay attention when matching NBits.
* We can have both truncation of extraction and widening of magic:
  https://rise4fun.com/Alive/XTw
  In other words, i don't believe we need to have any checks on
  bitwidths of any of these constructs.

This is worsened in general by the fact that we may have `sext` instead
of `zext` for shift amounts, and we don't yet canonicalize to `zext`,
although we should. I have not done anything about that here.

Also, we really should have something to weed out `sub` like these,
by folding them into `add` variant.

https://bugs.llvm.org/show_bug.cgi?id=42389

llvm-svn: 373964
2019-10-07 20:53:27 +00:00
Roman Lebedev 3da71714cb [InstCombine][NFC] Tests for "conditional sign-extend of high-bit-extract" pattern (PR42389)
https://bugs.llvm.org/show_bug.cgi?id=42389

llvm-svn: 373963
2019-10-07 20:53:16 +00:00
Roman Lebedev 0c73be590e [InstCombine] Move isSignBitCheck(), handle rest of the predicates
True, no test coverage is being added here. But those non-canonical
predicates that are already handled here already have no test coverage
as far as i can tell. I tried to add tests for them, but all the patterns
already get handled elsewhere.

llvm-svn: 373962
2019-10-07 20:53:08 +00:00
Roman Lebedev cb6d851bb6 [InstCombine][NFC] dropRedundantMaskingOfLeftShiftInput(): change how we deal with mask
Summary:
Currently, we pre-check whether we need to produce a mask or not.
This involves some rather magical constants.
I'd like to extend this fold to also handle the situation
when there's also a `trunc` before outer shift.
That will require another set of magical constants.
It's ugly.

Instead, we can just compute the mask, and check
whether mask is a pass-through (all-ones) or not.
This way we don't need to have any magical numbers.

This change is NFC other than the fact that we now compute
the mask and then check if we need (and can!) apply it.

Reviewers: spatel

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68470

llvm-svn: 373961
2019-10-07 20:53:00 +00:00
Roman Lebedev c3b394ffba [InstCombine] dropRedundantMaskingOfLeftShiftInput(): propagate undef shift amounts
Summary:
When we do `ConstantExpr::getZExt()`, that "extends" `undef` to `0`,
which means that for patterns a/b we'd assume that we must not produce
any bits for that channel, while in reality we simply didn't care
about that channel - i.e. we don't need to mask it.

Reviewers: spatel

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68239

llvm-svn: 373960
2019-10-07 20:52:52 +00:00
Cameron McInally 46d317fad4 [Bitcode] Update naming of UNOP_NEG to UNOP_FNEG
Differential Revision: https://reviews.llvm.org/D68588

llvm-svn: 373958
2019-10-07 20:41:25 +00:00
Jonas Devlieghere 61446a1421 [AccelTable] Remove stale comment (NFC)
rdar://55857228

llvm-svn: 373956
2019-10-07 20:33:20 +00:00
Nico Weber 0d19662a6a gn build: try to make system-libs.windows.test pass
llvm-svn: 373948
2019-10-07 19:17:02 +00:00
Matt Arsenault 538b73b797 AMDGPU/GlobalISel: Handle more G_INSERT cases
Start manually writing a table to get the subreg index. TableGen
should probably generate this, but I'm not sure what it looks like in
the arbitrary case where subregisters are allowed to not fully cover
the super-registers.

llvm-svn: 373947
2019-10-07 19:16:26 +00:00
Matt Arsenault 4bcdcad91b GlobalISel: Partially implement lower for G_INSERT
llvm-svn: 373946
2019-10-07 19:13:27 +00:00
Matt Arsenault 1237aa2996 AMDGPU/GlobalISel: Fix selection of 16-bit shifts
llvm-svn: 373945
2019-10-07 19:10:44 +00:00
Matt Arsenault 09ec6918bc AMDGPU/GlobalISel: Select VALU G_AMDGPU_FFBH_U32
llvm-svn: 373944
2019-10-07 19:10:43 +00:00
Matt Arsenault 0b2ea91d6d AMDGPU/GlobalISel: Use S_MOV_B64 for inline constants
This hides some defects in SIFoldOperands when the immediates are
split.

llvm-svn: 373943
2019-10-07 19:07:19 +00:00
Matt Arsenault 578fa2819f AMDGPU/GlobalISel: Widen 16-bit G_MERGE_VALUEs sources
Continue making a mess of merge/unmerge legality.

llvm-svn: 373942
2019-10-07 19:05:58 +00:00
Matt Arsenault b4cbf9862c AMDGPU/GlobalISel: Select more G_INSERT cases
At minimum handle the s64 insert type, which are emitted in real cases
during legalization.

We really need TableGen to emit something to emit something like the
inverse of composeSubRegIndices do determine the subreg index to use.

llvm-svn: 373938
2019-10-07 18:43:31 +00:00
Matt Arsenault 27269054d2 GlobalISel: Add target pre-isel instructions
Allows targets to introduce regbankselectable
pseudo-instructions. Currently the closet feature to this is an
intrinsic. However this requires creating a public intrinsic
declaration. This litters the public intrinsic namespace with
operations we don't necessarily want to expose to IR producers, and
would rather leave as private to the backend.

Use a new instruction bit. A previous attempt tried to keep using enum
value ranges, but it turned into a mess.

llvm-svn: 373937
2019-10-07 18:43:29 +00:00
Jordan Rose fdaa742174 Second attempt to add iterator_range::empty()
Doing this makes MSVC complain that `empty(someRange)` could refer to
either C++17's std::empty or LLVM's llvm::empty, which previously we
avoided via SFINAE because std::empty is defined in terms of an empty
member rather than begin and end. So, switch callers over to the new
method as it is added.

https://reviews.llvm.org/D68439

llvm-svn: 373935
2019-10-07 18:14:24 +00:00
Erich Keane 8a410bcef0 Fix Calling Convention through aliases
r369697 changed the behavior of stripPointerCasts to no longer include
aliases.  However, the code in CGDeclCXX.cpp's createAtExitStub counted
on the looking through aliases to properly set the calling convention of
a call.

The result of the change was that the calling convention mismatch of the
call would be replaced with a llvm.trap, causing a runtime crash.

Differential Revision: https://reviews.llvm.org/D68584

llvm-svn: 373929
2019-10-07 17:28:03 +00:00
Florian Hahn 90b7dc9e71 [Remarks] Pass StringBlockValue as StringRef.
After changing the remark serialization, we now pass StringRefs to the
serializer. We should use StringRef for StringBlockVal, to avoid
creating temporary objects, which then cause StringBlockVal.Value to
point to invalid memory.

Reviewers: thegameg, anemet

Reviewed By: thegameg

Differential Revision: https://reviews.llvm.org/D68571

llvm-svn: 373923
2019-10-07 17:05:09 +00:00
Wei Mi 283df8cf74 Fix build errors caused by rL373914.
llvm-svn: 373919
2019-10-07 16:45:47 +00:00
Wenlei He b3342e180e [llvm-profdata] Minor format fix
Summary: Minor format fix for output of "llvm-profdata -show"

Reviewers: wmi

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68440

llvm-svn: 373917
2019-10-07 16:30:31 +00:00
Simon Pilgrim 9c2e123043 [X86][SSE] getTargetShuffleInputs - move VT.isSimple/isVector checks inside. NFCI.
Stop all the callers from having to check the value type before calling getTargetShuffleInputs.

llvm-svn: 373915
2019-10-07 16:15:20 +00:00
Wei Mi b523790ae1 [SampleFDO] Add compression support for any section in ExtBinary profile format
Previously ExtBinary profile format only supports compression using zlib for
profile symbol list. In this patch, we extend the compression support to any
section. User can select some or all of the sections to compress. In an
experiment, for a 45M profile in ExtBinary format, compressing name table
reduced its size to 24M, and compressing all the sections reduced its size
to 11M.

Differential Revision: https://reviews.llvm.org/D68253

llvm-svn: 373914
2019-10-07 16:12:37 +00:00
Sanjay Patel b743f18b1f [LoopVectorize] add test that asserted after cost model change (PR43582); NFC
llvm-svn: 373913
2019-10-07 14:48:27 +00:00
David Greene a14ffc7eb7 Allow update_test_checks.py to not scrub names.
Add a --preserve-names option to tell the script not to replace IR names.
Sometimes tests want those names.  For example if a test is looking for a
modification to an existing instruction we'll want to make the names.

Differential Revision: https://reviews.llvm.org/D68081

llvm-svn: 373912
2019-10-07 14:37:20 +00:00
Kevin P. Neal 9f4de84eb0 Fix another sphinx warning.
Differential Revision:	https://reviews.llvm.org/D64746

llvm-svn: 373909
2019-10-07 14:14:46 +00:00
Amaury Sechet a6a70415c8 Regenerate ptr-rotate.ll . NFC
llvm-svn: 373908
2019-10-07 14:10:21 +00:00
Simon Atanasyan 55ac745828 [Mips] Always save RA when disabling frame pointer elimination
This ensures that frame-based unwinding will continue to work when
calling a noreturn function; there is not much use having the caller's
frame pointer saved if you don't also have the caller's program counter.

Patch by James Clarke.

Differential Revision: https://reviews.llvm.org/D68542

llvm-svn: 373907
2019-10-07 14:01:37 +00:00
Simon Atanasyan 19ede2f53b [Mips] Fix evaluating J-format branch targets
J/JAL/JALX/JALS are absolute branches, but stay within the current
256 MB-aligned region, so we must include the high bits of the
instruction address when calculating the branch target.

Patch by James Clarke.

Differential Revision: https://reviews.llvm.org/D68548

llvm-svn: 373906
2019-10-07 14:01:22 +00:00
whitequark b63db94fa5 [LLVM-C] Add bindings to create macro debug info
Summary: The C API doesn't have the bindings to create macro debug information.

Reviewers: whitequark, CodaFi, deadalnix

Reviewed By: whitequark

Subscribers: aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58334

llvm-svn: 373903
2019-10-07 13:57:13 +00:00
Kevin P. Neal a6fc72fba9 Fix sphinx warnings.
Differential Revision:	https://reviews.llvm.org/D64746

llvm-svn: 373902
2019-10-07 13:39:56 +00:00
Mirko Brkusanin b5fbdf1f5e Test commit
Fix comment.

llvm-svn: 373901
2019-10-07 13:23:12 +00:00
Kevin P. Neal 1c3d19c82d [FPEnv] Add constrained intrinsics for lrint and lround
Earlier in the year intrinsics for lrint, llrint, lround and llround were
added to llvm. The constrained versions are now implemented here.

Reviewed by:	andrew.w.kaylor, craig.topper, cameron.mcinally
Approved by:	craig.topper
Differential Revision:	https://reviews.llvm.org/D64746

llvm-svn: 373900
2019-10-07 13:20:00 +00:00
Nico Weber a1f5c258d6 gn build: use better triple on windows
The CMake build uses "x86_64-pc-windows-msvc". The "-msvc" suffix is
important because e.g. clang/test/lit.cfg.py matches against the
suffix "windows-msvc" to compute the presence of the "ms-sdk" and
the absence of the "LP64" feature.

Differential Revision: https://reviews.llvm.org/D68572

llvm-svn: 373899
2019-10-07 13:13:31 +00:00
Nico Weber 0fedc26a0d Revert r373888 "[IA] Recognize hexadecimal escape sequences"
It broke MC/AsmParser/directive_ascii.s on all bots:

    Assertion failed: (Index < Length && "Invalid index!"), function operator[],
        file ../../llvm/include/llvm/ADT/StringRef.h, line 243.

llvm-svn: 373898
2019-10-07 11:46:26 +00:00
Jay Foad 301decd93d [AMDGPU] Fix test checks
The GFX10-DENORM-STRICT checks were only passing by accident. Fix them
to make the test more robust in the face of scheduling or register
allocation changes.

llvm-svn: 373893
2019-10-07 10:57:41 +00:00
George Rimar 5ce8c39149 [llvm-readelf/llvm-objdump] - Improve/refactor the implementation of SHT_LLVM_ADDRSIG section dumping.
This patch:

* Adds a llvm-readobj/llvm-readelf test file for SHT_LLVM_ADDRSIG sections. (we do not have any)
* Enables dumping of SHT_LLVM_ADDRSIG with --all.
* Changes the logic to report a warning instead of an error when something goes wrong during dumping
  (allows to continue dumping SHT_LLVM_ADDRSIG and other sections on error).
* Refactors a piece of logic to a new toULEB128Array helper which might be used for GNU-style
  dumping implementation.

Differential revision: https://reviews.llvm.org/D68383

llvm-svn: 373890
2019-10-07 10:29:38 +00:00
Bill Wendling 6942327a8f [IA] Recognize hexadecimal escape sequences
Summary:
Implement support for hexadecimal escape sequences to match how GNU 'as'
handles them. I.e., read all hexadecimal characters and truncate to the
lower 16 bits.

Reviewers: nickdesaulniers

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68483

llvm-svn: 373888
2019-10-07 09:54:53 +00:00
James Molloy beb696e2a6 [TableGen] Pacify gcc-5.4 more
Followup to a previous pacification, this performs the same workaround
to the TableGen generated code for tuple automata.

llvm-svn: 373883
2019-10-07 08:23:20 +00:00
Martin Storsjo dfc1aee25b Revert "[SLP] avoid reduction transform on patterns that the backend can load-combine"
This reverts SVN r373833, as it caused a failed assert "Non-zero loop
cost expected" on building numerous projects, see PR43582 for details
and reproduction samples.

llvm-svn: 373882
2019-10-07 08:21:37 +00:00
Djordje Todorovic 0c56f425a0 [llvm-locstats] Fix a typo in the documentation; NFC
llvm-svn: 373880
2019-10-07 07:31:49 +00:00
Craig Topper 6785108356 [X86] Autogenerate checks in leaFixup32.mir and leaFixup64.mir. NFC
llvm-svn: 373878
2019-10-07 06:50:56 +00:00
Craig Topper 2c4f078877 [X86] Support LEA64_32r in processInstrForSlow3OpLEA and use INC/DEC when possible.
Move the erasing and iterator updating inside to match the
other slow LEA function.

I've adapted code from optTwoAddrLEA and basically rebuilt the
implementation here. We do lose the kill flags now just like
optTwoAddrLEA. This runs late enough in the pipeline that
shouldn't really be a problem.

llvm-svn: 373877
2019-10-07 06:27:55 +00:00