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1792 Commits

Author SHA1 Message Date
Jim Grosbach 70532e289f Thumb2 parsing and encoding for CLZ. 
llvm-svn: 139177
 2011-09-06 20:44:17 +00:00
Jim Grosbach 803898f119 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Owen Anderson b041e866b0 Port more encoding tests over to Thumb2 decoding tests. 
llvm-svn: 139171
 2011-09-06 20:26:34 +00:00
Jim Grosbach 6952281037 Thumb2 parsing and encoding for CDP/CDP2. 
llvm-svn: 139168
 2011-09-06 20:12:23 +00:00
Jim Grosbach f347d1d772 Thumb2 parsing and encoding for CBZ/CBNZ. 
llvm-svn: 139054
 2011-09-02 23:46:10 +00:00
Jim Grosbach 34842ceb97 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach 9e55023ca7 Thumb2 parsing and encoding for BIC. 
llvm-svn: 139052
 2011-09-02 23:37:54 +00:00
Jim Grosbach 93e3fd29b2 Thumb2 parsing and encoding for BFI. 
llvm-svn: 139051
 2011-09-02 23:28:46 +00:00
Jim Grosbach be31448d99 Thumb2 parsing and encoding for BFC. 
llvm-svn: 139050
 2011-09-02 23:25:46 +00:00
Jim Grosbach a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jim Grosbach a216debb37 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Kevin Enderby 5b03f72292 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach 370e923434 Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jim Grosbach 2761155203 Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Kevin Enderby 54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Jim Grosbach b861b2b475 Tests for Thumb2 AND (immediate) instruction. 
llvm-svn: 139013
 2011-09-02 17:44:27 +00:00
Jim Grosbach c302f5cce7 Add FIXME. Thumb2 ADR encoding choice is non-trivial. 
llvm-svn: 139008
 2011-09-02 17:21:59 +00:00
Craig Topper 94ce535647 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. 
llvm-svn: 138997
 2011-09-02 04:17:54 +00:00
Jim Grosbach f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Owen Anderson 35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Owen Anderson a455a0b1e7 Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Jim Grosbach 6a69d6902f Run the Thumb1 parser tests in Thumb2 mode, as well. 
Thumb2 is a superset of Thumb1, so all of the encodings should still work.

llvm-svn: 138883
 2011-08-31 19:50:28 +00:00
Jim Grosbach 6eb213c919 Thumb NOP encoding varies depending on ARCH revision. 
llvm-svn: 138876
 2011-08-31 18:35:46 +00:00
Owen Anderson 5c160fd243 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Jim Grosbach af8c3cc710 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Jim Grosbach 6d606fbe14 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Owen Anderson 2fa06a7226 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson fdf3cd7f2b Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Owen Anderson d16fb43b1f Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson 543c89fb15 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Owen Anderson 2e282257ed Port Thumb2 assembler tests over to disassembler tests. 
llvm-svn: 138822
 2011-08-30 20:03:11 +00:00
Craig Topper 4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
llvm-svn: 138795
 2011-08-30 07:09:35 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach 4b23a65582 Remove redundant tests from XFAIL'ed test file. 
llvm-svn: 138779
 2011-08-29 23:04:04 +00:00
Jim Grosbach 55d6f43cab Thumb2 assembly parsing and encoding support for ADC(immediate). 
llvm-svn: 138778
 2011-08-29 23:01:38 +00:00
Jim Grosbach 89a12be8bb Remove test file. Superceded by other more exhaustive tests. 
llvm-svn: 138777
 2011-08-29 23:00:19 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Kevin Enderby 7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Owen Anderson f02d98d7c0 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Owen Anderson b205c029a4 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
llvm-svn: 138675
 2011-08-26 23:32:08 +00:00
Owen Anderson 6c70e58041 Correct encoding of BL with immediate offset. 
llvm-svn: 138673
 2011-08-26 22:54:51 +00:00
Owen Anderson 16d33f36d5 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Owen Anderson a01bcbfc80 Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. 
llvm-svn: 138635
 2011-08-26 18:09:22 +00:00
Owen Anderson f3b6507e26 Add a testcase for r138625. 
llvm-svn: 138626
 2011-08-26 06:45:08 +00:00
Craig Topper c66d50d1a2 Fix disassembling of VCVTSD2SI 
llvm-svn: 138623
 2011-08-26 04:49:29 +00:00
Owen Anderson 5e30972cff Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed. 
llvm-svn: 138575
 2011-08-25 18:30:18 +00:00
Craig Topper 76e3e0b554 Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. 
llvm-svn: 138552
 2011-08-25 07:42:00 +00:00
Craig Topper e1541838f9 Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723. 
llvm-svn: 138551
 2011-08-25 06:57:46 +00:00
Evan Cheng eee864520c Some autoconf tests use module level inline asm to test compiler's handling of 
.cfi_startproc. e.g. libffi:

 $ cat confopt.c 
asm (".cfi_startproc\n\t.cfi_endproc");

int main () { return 0; }

Teach MC / dwarf emission to handle these cfi directives which essentially
create an empty frame.

rdar://10017184

llvm-svn: 138504
 2011-08-24 22:31:37 +00:00
Jim Grosbach b2a2c031b8 Update tests for 138501. 
llvm-svn: 138502
 2011-08-24 22:30:18 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
 2011-08-24 21:42:27 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Owen Anderson 16fd0d96f2 Port over more encoding tests to decoding tests. 
llvm-svn: 138441
 2011-08-24 17:08:34 +00:00
Jim Grosbach 37563cd545 Thumb parsing and encoding for WFE, WFI and YIELD. 
llvm-svn: 138364
 2011-08-23 20:02:30 +00:00
Jim Grosbach ad9e8655ee Thumb parsing and encoding for UXTB and UXTH. 
llvm-svn: 138363
 2011-08-23 19:59:32 +00:00
Jim Grosbach 5e4ea175f6 Thumb parsing and encoding for TST. 
llvm-svn: 138362
 2011-08-23 19:53:17 +00:00
Jim Grosbach bb07e73e0d Thumb parsing and encoding for SXTB and SXTH. 
llvm-svn: 138361
 2011-08-23 19:51:42 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC. 
llvm-svn: 138360
 2011-08-23 19:49:10 +00:00
Jim Grosbach d88404fbaa Thumb parsing and encoding for SUB. 
llvm-svn: 138359
 2011-08-23 19:45:45 +00:00
Jim Grosbach f1ca6a6df6 Thumb parsing and encoding for STRH. 
llvm-svn: 138352
 2011-08-23 18:56:20 +00:00
Jim Grosbach 635aa69a91 Thumb parsing and encoding for STRB. 
llvm-svn: 138349
 2011-08-23 18:43:06 +00:00
Jim Grosbach 505be75900 Thumb parsing and encoding for tSTRspi. 
llvm-svn: 138348
 2011-08-23 18:39:41 +00:00
Jim Grosbach 6e546e0725 Thumb parsing and encoding for STR. 
Not including tSTRspi.

llvm-svn: 138347
 2011-08-23 18:33:38 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Owen Anderson 924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Owen Anderson 041dba6dec Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
llvm-svn: 138337
 2011-08-23 17:37:32 +00:00
Owen Anderson dcea63236e Port more assemble tests over to disassembly tests. 
llvm-svn: 138336
 2011-08-23 17:26:35 +00:00
Jim Grosbach cc9d792ec1 Thumb parsing and encoding for SETEND. 
llvm-svn: 138312
 2011-08-22 23:58:02 +00:00
Jim Grosbach 3636be3c8f Thumb parsing and encoding for SBC. 
llvm-svn: 138311
 2011-08-22 23:55:58 +00:00
Jim Grosbach c3c32d9e09 Thumb parsing and encoding for RSB. 
llvm-svn: 138308
 2011-08-22 23:47:13 +00:00
Jim Grosbach 73661b8a37 Thumb parsing and encoding for ROR. 
llvm-svn: 138304
 2011-08-22 23:40:51 +00:00
Jim Grosbach a9d88df987 Thumb parsing and encoding for REV/REV16/REVSH. 
llvm-svn: 138303
 2011-08-22 23:39:25 +00:00
Owen Anderson 1346d79b4b t2SMLAD is a four-register instruction, not a three-register one. 
llvm-svn: 138301
 2011-08-22 23:31:45 +00:00
Owen Anderson f94b7b7d57 Correct operand naming of t2USAT16 to allow proper decoding. 
llvm-svn: 138300
 2011-08-22 23:27:47 +00:00
Owen Anderson 5e9989a920 Match operand naming to allow correct decoding of t2LDRSH_POST. 
llvm-svn: 138298
 2011-08-22 23:22:05 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Jim Grosbach 096423b6be Tidy up. Trailing whitespace. 
llvm-svn: 138293
 2011-08-22 23:13:54 +00:00
Owen Anderson a743409ec8 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
llvm-svn: 138292
 2011-08-22 23:10:16 +00:00
Jim Grosbach 40da063178 Thumb parsing and encoding for PUSH. 
llvm-svn: 138290
 2011-08-22 23:05:11 +00:00
Jim Grosbach 5507203262 Fix think-o. 
llvm-svn: 138288
 2011-08-22 23:04:26 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Jim Grosbach 0869b900cc Thumb assembly parsing and encoding for POP. 
llvm-svn: 138286
 2011-08-22 23:00:19 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
llvm-svn: 138273
 2011-08-22 21:34:00 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00
Owen Anderson 721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Owen Anderson ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Owen Anderson fe29fe431d Port another swathe of Thumb1 encoding tests over to decoding tests. 
llvm-svn: 138250
 2011-08-22 18:05:49 +00:00
Owen Anderson b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Jim Grosbach aa42847164 Thumb assembly parsing and encoding for ORR. 
llvm-svn: 138245
 2011-08-22 17:41:44 +00:00
Jim Grosbach bd16424f91 Fix AsmParser binary precedence for shift operators. 
rdar://9976729

llvm-svn: 138208
 2011-08-20 16:24:13 +00:00
Jim Grosbach 3322f02a03 Tidy up. Whitespace. 
llvm-svn: 138207
 2011-08-20 16:10:09 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes d126347f32 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Jim Grosbach fd4de3aeff Thumb assembly parsing and encoding for MVN. 
llvm-svn: 138109
 2011-08-19 22:09:23 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Jim Grosbach d07e104844 Add FIXME. 
llvm-svn: 138077
 2011-08-19 20:48:54 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach 1eb6eb0955 Thumb assembly parsing and encoding for LSR. 
llvm-svn: 138065
 2011-08-19 19:34:22 +00:00
Jim Grosbach 3245520ade Thumb assembly parsing and encoding for LSL(register). 
llvm-svn: 138064
 2011-08-19 19:30:58 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach 106281f329 Thumb assembly parsing and encoding for LDR(register). 
llvm-svn: 138056
 2011-08-19 18:35:06 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Craig Topper ba6c2a52c7 Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
llvm-svn: 138034
 2011-08-19 05:28:50 +00:00
Bruno Cardoso Lopes 22241acc29 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Owen Anderson 627021d7c0 More Thumb1 decoding tests. 
llvm-svn: 137974
 2011-08-18 20:05:06 +00:00
Jim Grosbach 6cb336cb09 Thumb assembly parsing and encoding for EOR. 
llvm-svn: 137964
 2011-08-18 18:10:38 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
James Molloy 9f9371ccb3 Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
llvm-svn: 137960
 2011-08-18 18:03:02 +00:00
Jim Grosbach 47bf39d921 Thumb assembly parsing and encoding test for CMN. 
llvm-svn: 137957
 2011-08-18 17:55:03 +00:00
Owen Anderson ec3884c50a Port over BL/BLX to disassembly tests. 
llvm-svn: 137954
 2011-08-18 17:43:52 +00:00
Jim Grosbach 0081879ee7 ARM assembly parsing and encoding test for BX/BLX (register). 
llvm-svn: 137949
 2011-08-18 17:02:28 +00:00
Jim Grosbach 8b7158e557 ARM assembly parsing and encoding test for BL/BLX (immediate). 
llvm-svn: 137948
 2011-08-18 17:00:09 +00:00
Owen Anderson a90896397b Port new Thumb1 encoding tests over to decoding tests. 
llvm-svn: 137902
 2011-08-17 23:37:33 +00:00
Jim Grosbach 1b43828958 ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach e3bdcd0ea8 ARM assembly parsing and encoding test for BIC. 
llvm-svn: 137895
 2011-08-17 23:00:53 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Jim Grosbach e2a0404a69 Thumb assembly parsing and encoding for ADR. 
llvm-svn: 137864
 2011-08-17 20:37:40 +00:00
Jim Grosbach e2d152016f Add a couple of FIXMEs. 
llvm-svn: 137861
 2011-08-17 20:35:57 +00:00
Owen Anderson d40d838cc4 Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
llvm-svn: 137840
 2011-08-17 18:21:36 +00:00
Jim Grosbach 80636b48c0 Thumb assembly parsing and encoding for ADC(register) instruction. 
llvm-svn: 137833
 2011-08-17 17:55:28 +00:00
Jim Grosbach a806eebe13 Add missing '@' delimiter. 
llvm-svn: 137832
 2011-08-17 17:46:01 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Jim Grosbach 2c21bf4b43 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00
Jim Grosbach d3ad0aa413 Tidy up formatting. 
llvm-svn: 137747
 2011-08-16 20:55:41 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Owen Anderson 53440984b3 Add a test file for Thumb2 NEON. 
llvm-svn: 137687
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes 67005029bc Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684
 2011-08-15 23:36:45 +00:00
Owen Anderson 5286bd2d01 Add some more comprehensive VFP decoding tests. 
llvm-svn: 137657
 2011-08-15 21:29:01 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson 944f4923a4 Add a test for Thumb1 LDRSH decoding. 
llvm-svn: 137645
 2011-08-15 20:15:43 +00:00
Owen Anderson f746b0ec53 Add testcase for STRH. Patch by James Molloy. 
llvm-svn: 137644
 2011-08-15 20:12:03 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson ed6d3e813e Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
llvm-svn: 137495
 2011-08-12 19:42:45 +00:00
Jim Grosbach d1b60f7a6d Tidy up formatting. 
llvm-svn: 137471
 2011-08-12 17:43:31 +00:00
Jim Grosbach 234317d12a Tidy up formatting. 
llvm-svn: 137464
 2011-08-12 17:01:02 +00:00
Benjamin Kramer 91ea511436 MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
llvm-svn: 137414
 2011-08-12 01:51:29 +00:00
Jim Grosbach 1978ddf769 Clean up formatting a bit. 
llvm-svn: 137393
 2011-08-11 23:57:17 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Jim Grosbach aa07cb6a98 Fix tests per now-correct encoding as of r137371. 
llvm-svn: 137376
 2011-08-11 22:31:48 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Jim Grosbach 7db3bfbd45 ARM STRHT assembly parsing and encoding. 
llvm-svn: 137358
 2011-08-11 21:39:41 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach d0767f37c1 Add FIXME. 
llvm-svn: 137336
 2011-08-11 19:43:42 +00:00
Jim Grosbach 295788756d ARM STRB assembly parsing and encoding tests. 
llvm-svn: 137335
 2011-08-11 19:42:58 +00:00
Jim Grosbach 14a4164206 Fix a copy/paste error so that LDRB(register) actually gets tested. 
llvm-svn: 137333
 2011-08-11 19:34:23 +00:00
Jim Grosbach 06b7f0c901 ARM STR(register) assembly parsing and encoding tests. 
llvm-svn: 137332
 2011-08-11 19:26:17 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Jim Grosbach 94ba2cba6e ARM tests for LDRSHT assembly parsing and encoding. 
llvm-svn: 137274
 2011-08-10 23:18:30 +00:00
Jim Grosbach a6ab52bf9f ARM tests for LDRSH assembly parsing and encoding. 
llvm-svn: 137272
 2011-08-10 23:12:25 +00:00
Jim Grosbach 2953404723 ARM tests for LDRSBT assembly parsing and encoding. 
llvm-svn: 137271
 2011-08-10 23:08:56 +00:00
Jim Grosbach c11bbf3bda ARM tests for LDRSB assembly parsing and encoding. 
llvm-svn: 137270
 2011-08-10 23:06:44 +00:00
Jim Grosbach 35cdf36c32 Add FIXME. 
llvm-svn: 137265
 2011-08-10 22:56:43 +00:00
Jim Grosbach 5e0c9711f2 ARM tests for LDRHT assembly parsing and encoding. 
llvm-svn: 137263
 2011-08-10 22:55:38 +00:00
Jim Grosbach 7cd4253cc3 ARM tests for LDRH(register) assembly parsing and encoding. 
llvm-svn: 137261
 2011-08-10 22:45:42 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach ae1b002fa3 Add FIXME 
llvm-svn: 137258
 2011-08-10 22:20:38 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
llvm-svn: 137189
 2011-08-10 00:03:03 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands. 
llvm-svn: 137180
 2011-08-09 23:33:27 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions. 
llvm-svn: 137176
 2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions. 
llvm-svn: 137172
 2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
llvm-svn: 137168
 2011-08-09 22:48:45 +00:00
Benjamin Kramer 406dc1755f ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
 2011-08-09 22:02:50 +00:00
Owen Anderson 7a2401dbf0 Tighten Thumb1 branch predicate decoding. 
llvm-svn: 137146
 2011-08-09 21:07:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Jim Grosbach 5838c0c47e ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach f6dbc3a57c Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00
Jim Grosbach 0f2dd284e9 Add ARM LDR parsing tests. 
llvm-svn: 136977
 2011-08-05 20:33:39 +00:00
Rafael Espindola 77dde89b90 Fix the bitwidth of the remaining fields. 
llvm-svn: 136884
 2011-08-04 17:00:11 +00:00
Rafael Espindola 9bc32a96be print st_shndx with the correct number of bits. 
llvm-svn: 136880
 2011-08-04 15:50:13 +00:00
Rafael Espindola 9528995e3f print st_other with the correct number of bits. 
llvm-svn: 136877
 2011-08-04 15:38:19 +00:00
Rafael Espindola 96df560ce1 print st_type with the correct number of bits. 
llvm-svn: 136875
 2011-08-04 15:24:00 +00:00
Rafael Espindola 79ef75dc49 Print st_bind with the correct number of bits. 
llvm-svn: 136874
 2011-08-04 15:10:35 +00:00
Rafael Espindola 1848231ad1 Print r_sym with the correct number of bits. 
llvm-svn: 136873
 2011-08-04 14:48:27 +00:00
Rafael Espindola 260af5cef6 Print r_type with the correct number of bits. 
llvm-svn: 136872
 2011-08-04 14:39:30 +00:00
Rafael Espindola 1b282e7e49 Another counter goes decimal. 
llvm-svn: 136871
 2011-08-04 14:27:46 +00:00
Rafael Espindola 65c559c5fb Change anther counter to decimal. 
llvm-svn: 136870
 2011-08-04 14:01:03 +00:00
Rafael Espindola cad9e7f094 Don't print a counter in hex. 
llvm-svn: 136869
 2011-08-04 13:39:15 +00:00
Rafael Espindola 69c67d3b18 Print all the bits in the addend. 
llvm-svn: 136867
 2011-08-04 13:00:24 +00:00
Jason W Kim e4df09f7ba Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

llvm-svn: 136855
 2011-08-04 00:38:45 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
 2011-08-03 23:50:40 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
 2011-07-29 20:26:09 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction. 
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
 2011-07-29 18:47:24 +00:00
Jim Grosbach 1c1d2438aa ARM update tests for CPS instruction. 
llvm-svn: 136472
 2011-07-29 17:39:27 +00:00
Jim Grosbach b9bebc1b03 CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them. 
llvm-svn: 136408
 2011-07-28 21:59:38 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate). 
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
 2011-07-28 21:57:55 +00:00
Jim Grosbach 7f45559e86 Remove obsolete FIXME reference in comment. 
llvm-svn: 136400
 2011-07-28 21:37:05 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI. 
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
 2011-07-28 21:34:26 +00:00
Jim Grosbach 8b3184e540 ARM parsing and encoding for ADR. 
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
 2011-07-28 16:33:54 +00:00
Jim Grosbach 4356636fc0 Update ARM tests for parsing and encoding of WFE, WFI and YIELD. 
llvm-svn: 136358
 2011-07-28 16:00:41 +00:00
Jim Grosbach 4059137f56 ARM parsing and encoding tests. 
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312
 2011-07-28 00:37:03 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
 2011-07-27 23:22:03 +00:00
Jim Grosbach e37f7dc349 ARM assembly parsing and encoding for USUB16 and USUB8. 
llvm-svn: 136289
 2011-07-27 23:10:05 +00:00
Jim Grosbach 05f80d3add ARM assembly parsing and encoding for USAX. 
llvm-svn: 136288
 2011-07-27 23:07:00 +00:00
Kevin Enderby 5ef6c453a6 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
 2011-07-27 23:01:50 +00:00
Jim Grosbach 16dd4adcbe Clean up tabs. 
llvm-svn: 136286
 2011-07-27 22:35:06 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16. 
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
 2011-07-27 22:34:17 +00:00
Jim Grosbach fea7a44a9b ARM assembly parsing and encoding tests for USAD8 and USADA8. 
llvm-svn: 136284
 2011-07-27 22:23:02 +00:00
Jim Grosbach 1644409b47 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. 
llvm-svn: 136282
 2011-07-27 22:13:08 +00:00
Jim Grosbach 1a3ddffc1c Fix comment copy/paste-o. 
llvm-svn: 136281
 2011-07-27 22:11:41 +00:00
Jim Grosbach 84ecab228a ARM assembly parsing and encoding tests for UQASX and UQSAX. 
llvm-svn: 136280
 2011-07-27 22:09:30 +00:00
Jim Grosbach 928f4175c0 ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
llvm-svn: 136279
 2011-07-27 22:08:14 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
 2011-07-27 22:01:42 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
 2011-07-27 21:58:11 +00:00
Jim Grosbach 121c21aba9 ARM assembly parsing and encoding tests for UMAAL. 
llvm-svn: 136272
 2011-07-27 21:53:42 +00:00
Jim Grosbach 7cfd32a006 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
llvm-svn: 136267
 2011-07-27 21:21:59 +00:00
Jim Grosbach 3f45383ef5 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
llvm-svn: 136266
 2011-07-27 21:20:45 +00:00
Jim Grosbach 03f56d9de6 ARM parsing and encoding of SBFX and UBFX. 
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].

llvm-svn: 136264
 2011-07-27 21:09:25 +00:00
Jim Grosbach 36ce7492a6 ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX. 
llvm-svn: 136261
 2011-07-27 20:43:44 +00:00
Jim Grosbach 542333ea05 ARM assembly parsing and encoding tests for TST instruction. 
llvm-svn: 136260
 2011-07-27 20:38:58 +00:00
Jim Grosbach f176e1addb ARM assembly parsing and encoding tests for TEQ instruction. 
llvm-svn: 136259
 2011-07-27 20:37:36 +00:00
Owen Anderson fa9e6d43a0 Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. 
llvm-svn: 136255
 2011-07-27 20:29:48 +00:00
Jim Grosbach 833b9d3353 ARM assembly parsing and encoding for extend instructions. 
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.

llvm-svn: 136252
 2011-07-27 20:15:40 +00:00
Jim Grosbach edaa35ae6f ARM diagnostics for ldrexd/stredx out of order paired register operands. 
llvm-svn: 136110
 2011-07-26 18:25:39 +00:00
Jim Grosbach 4e895470bd ARM parsing and encoding tests for load/store exclusive instructions. 
llvm-svn: 136105
 2011-07-26 18:07:21 +00:00
Jim Grosbach 15e8d74231 ARM assembly parsing and encoding for SWP[B] instructions. 
llvm-svn: 136098
 2011-07-26 17:15:11 +00:00
Jim Grosbach f16378479b ARM parsing and encoding for SVC instruction. 
llvm-svn: 136090
 2011-07-26 16:24:27 +00:00
Jim Grosbach 2c374c4fb6 ARM assembly parsing and encoding tests for SUB instruction. 
llvm-svn: 136089
 2011-07-26 15:44:05 +00:00
Jim Grosbach dc45f00cf5 Update ARM STM tests. Fix check: prefix for diagnostic tests. 
llvm-svn: 136088
 2011-07-26 15:41:22 +00:00
Jim Grosbach 9becc53e32 ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8. 
llvm-svn: 136013
 2011-07-25 23:32:14 +00:00
Jim Grosbach 475c6dbef6 ARM assembly parsing and encoding for SSAT16 instruction. 
llvm-svn: 136006
 2011-07-25 23:09:14 +00:00
Jim Grosbach 3a9cbeed73 ARM assembly parsing and encoding for SSAT instruction. 
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').

Add tests for diagnostics and proper encoding.

llvm-svn: 135990
 2011-07-25 22:20:28 +00:00
Jim Grosbach 38b1ed8ce2 Move some ELF directives into ELF asm parser. 
The .local, .hidden, .internal, and .protected are not legal for all supported
file formats (in particular, they're invalid for MachO). Move the parsing for
them into the ELF assembly parser since that's the format they're for.
Similarly, .weak is used by COFF and ELF, but not MachO, so move the parsing
to the COFF and ELF asm parsers. Previously, using any of these directives
on Darwin would result in an assertion failure in the parser; now we get
a diagnostic as we should.

rdar://9827089

llvm-svn: 135921
 2011-07-25 17:55:35 +00:00
Jim Grosbach d69b3423a8 Add FIXME 
llvm-svn: 135819
 2011-07-22 22:15:38 +00:00
Jim Grosbach bc5d709ad9 ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX. 
llvm-svn: 135818
 2011-07-22 22:13:00 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
 2011-07-22 22:06:05 +00:00
Jim Grosbach 999afadffa ARM assembly parsing and encoding tests. 
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.

llvm-svn: 135810
 2011-07-22 21:34:56 +00:00
Jim Grosbach 5b84e16503 ARM assembly parsing and encoding tests for SMLAWB/SMLAWT. 
llvm-svn: 135800
 2011-07-22 20:51:24 +00:00
Jim Grosbach e2220221a2 ARM assembly parsing and encoding tests. 
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.

llvm-svn: 135798
 2011-07-22 20:30:40 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
 2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.

llvm-svn: 135796
 2011-07-22 20:11:20 +00:00
Jim Grosbach 0b28f0cca2 ARM testcases for assembly parsing and encoding SMLA* instructions. 
llvm-svn: 135795
 2011-07-22 20:01:34 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction. 
llvm-svn: 135782
 2011-07-22 18:13:31 +00:00
Jim Grosbach 24ace20824 ARM encoding and assembly parsing tests. 
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.

llvm-svn: 135780
 2011-07-22 18:04:48 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
 2011-07-22 17:44:50 +00:00
Jim Grosbach 4535b9194a ARM assembly parsing and encoding tests for SEL instruction. 
llvm-svn: 135772
 2011-07-22 16:59:33 +00:00
Jim Grosbach 3354674b48 ARM parsing and encoding tests for SBC instruction. 
llvm-svn: 135718
 2011-07-21 23:03:59 +00:00
Jim Grosbach 8dbf59d041 ARM testcases for SADD/SASX parsing and encoding. 
llvm-svn: 135715
 2011-07-21 23:00:49 +00:00
Jim Grosbach 2a0320c877 ARM assembly parsing support for RSC instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135713
 2011-07-21 22:56:30 +00:00
Jim Grosbach 17806e6636 ARM assembly parsing support for RSB instruction. 
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.

llvm-svn: 135712
 2011-07-21 22:37:43 +00:00
Jim Grosbach 2a22c06267 ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH. 
llvm-svn: 135710
 2011-07-21 22:29:23 +00:00
Jim Grosbach b31e60b7c6 ARM parsing and encodings tests for saturating arithmetic insns. 
llvm-svn: 135709
 2011-07-21 22:18:28 +00:00
Jim Grosbach 0a8d89242f ARM assembly parsing POP/PUSH mnemonics. 
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.

llvm-svn: 135702
 2011-07-21 19:57:11 +00:00
Jim Grosbach b2aa2c4a24 Add tests for ARM PKH assembly parsing. 
llvm-svn: 135696
 2011-07-21 19:02:03 +00:00
Eli Friedman ae60b6b008 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. 
llvm-svn: 135607
 2011-07-20 19:36:11 +00:00
Jim Grosbach 2ea9f25f5f Add parsing/encoding tests for ARM ORR instruction. 
llvm-svn: 135602
 2011-07-20 18:48:53 +00:00
Jim Grosbach a3fcb962eb Consolidate ARM NOP encoding test. 
llvm-svn: 135600
 2011-07-20 18:39:38 +00:00
Jim Grosbach 614e90a126 ARM parsing and encoding tests for MVN 
llvm-svn: 135599
 2011-07-20 18:37:08 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction. 
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
 2011-07-20 18:20:31 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction. 
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
 2011-07-19 22:45:10 +00:00
Jim Grosbach 97094d8f06 ARM assembly parsing of MRS instruction. 
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
 2011-07-19 21:59:29 +00:00
Jim Grosbach 7d1e5f11ea ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. 
Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521
 2011-07-19 20:35:35 +00:00
Jim Grosbach b17d9b12a6 Move mr[r]c[2] ARM tests and tidy up a bit. 
llvm-svn: 135517
 2011-07-19 20:28:56 +00:00
Jim Grosbach 69721dce67 ARM testcases for MOVT. 
llvm-svn: 135516
 2011-07-19 20:23:25 +00:00
Jim Grosbach 5cc3b4cd9a ARM assembly parsing for MOV (register). 
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513
 2011-07-19 20:10:31 +00:00
Jim Grosbach 7c09e3c3f3 ARM assembly parsing for MOV (immediate). 
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500
 2011-07-19 19:13:28 +00:00
Jim Grosbach 20dd6e9fae Whitespace. 
llvm-svn: 135499
 2011-07-19 19:02:39 +00:00
Eli Friedman 0318036c4d Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. 
llvm-svn: 135337
 2011-07-16 02:41:28 +00:00
Eli Friedman 3846acc98e PR10370: Make sure we know how to relax push correctly on x86-64. 
llvm-svn: 135303
 2011-07-15 21:28:39 +00:00
Owen Anderson 454e1c7abb Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
llvm-svn: 135290
 2011-07-15 18:46:47 +00:00
Jim Grosbach 03a8a16f32 ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203
 2011-07-14 22:04:21 +00:00
Jim Grosbach 51849920f1 Add some testcases for ARM MLA/MLS instructions. 
llvm-svn: 135196
 2011-07-14 21:43:05 +00:00
Jim Grosbach 26e7449443 ARM MCRR/MCRR2 immediate operand range checking. 
llvm-svn: 135192
 2011-07-14 21:26:42 +00:00
Jim Grosbach d37d2025e9 ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
 2011-07-14 21:19:17 +00:00
Jim Grosbach e336a290a6 Enable some tests we now handle correctly. 
llvm-svn: 135185
 2011-07-14 21:02:23 +00:00
Jim Grosbach 2f9aeeef3b Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
 2011-07-14 18:35:38 +00:00
Jim Grosbach d616cf3497 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Jim Grosbach b218202586 ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
 2011-07-14 18:00:31 +00:00
Jim Grosbach e6f8b1fac6 ARM tests for EOR instruction parsing and encoding. 
llvm-svn: 135119
 2011-07-14 00:22:21 +00:00
Jim Grosbach f34e35da1c Remove duplicate tests. 
llvm-svn: 135117
 2011-07-14 00:19:19 +00:00
Jim Grosbach a0958d7abf ARM Assembler support for DSB instruction. 
Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116
 2011-07-14 00:18:13 +00:00
Jim Grosbach 44c3f08e85 ARM Assembler support for DMB instruction. 
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109
 2011-07-13 23:40:38 +00:00
Jim Grosbach 507ba77465 ARM Assembler support for DBG instruction. 
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
 2011-07-13 22:59:38 +00:00
Jim Grosbach 307de01867 ARM parsing and encoding tests for CMN/CMP. 
llvm-svn: 135098
 2011-07-13 22:26:58 +00:00
Jim Grosbach 9559d360e5 Shuffle ARM assembly tests a bit. 
llvm-svn: 135095
 2011-07-13 22:19:10 +00:00
Jim Grosbach 31756c2283 Range checking for CDP[2] immediates. 
llvm-svn: 135092
 2011-07-13 22:01:08 +00:00
Jim Grosbach adb29b6dbb Fix predicates for Thumb co-processor instructions. 
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
 2011-07-13 21:14:23 +00:00
Jim Grosbach ec8989115d Testcases for ARM assembly BX/BXJ instructions. 
llvm-svn: 135078
 2011-07-13 20:25:46 +00:00
Jim Grosbach 2371a3f14a Testcases for ARM assembly BLX/BL instructions. 
llvm-svn: 135072
 2011-07-13 20:11:04 +00:00
Jim Grosbach 975b641ee8 Range checking for 16-bit immediates in ARM assembly. 
llvm-svn: 135071
 2011-07-13 20:10:10 +00:00
Jim Grosbach c845e55374 Add tests for ARM parsing of 'BKPT' instruction. 
llvm-svn: 135063
 2011-07-13 19:17:36 +00:00
Jim Grosbach 43b45e2790 Fix copy-pasto. 
llvm-svn: 135062
 2011-07-13 19:16:30 +00:00
Jim Grosbach 4f0f2ac757 Add tests for ARM parsing of 'BIC' instruction. 
llvm-svn: 135061
 2011-07-13 19:12:32 +00:00
Jim Grosbach 6cfb1573bf Add some FIXMEs. 
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.

llvm-svn: 135060
 2011-07-13 19:10:23 +00:00
Jim Grosbach b7cdd8772c Add tests for ARM parsing of 'AND' instruction. 
llvm-svn: 135056
 2011-07-13 18:55:14 +00:00
Jim Grosbach bb24c595f7 Improve ARM assembly parsing diagnostics a bit. 
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
 2011-07-13 18:49:30 +00:00
Jim Grosbach 61a9f2af9e Add tests for ARM parsing of 'ADD' instruction 
llvm-svn: 135053
 2011-07-13 18:12:46 +00:00
Jim Grosbach 04afb071e1 Destination register operand is optional for ADC and SBC ARM. 
llvm-svn: 135052
 2011-07-13 17:57:17 +00:00
Jim Grosbach 7dcd1354f1 Flesh out ARM Parser support for shifted-register operands. 
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
 2011-07-13 17:50:29 +00:00
Jim Grosbach 992a2856f5 Add check for predicate w/o S bit. 
llvm-svn: 134987
 2011-07-12 16:25:04 +00:00
Jim Grosbach a9a3f0a414 Fix recognition of ARM 'adcs' mnemonic. 
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
 2011-07-11 17:09:57 +00:00
Jim Grosbach 581da64241 Simplify printing of ARM shifted immediates. 
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
 2011-07-11 16:48:36 +00:00
Evan Cheng c5e6d2f519 - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo 
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
 2011-07-11 03:57:24 +00:00
Evan Cheng 284b467d9f Add support for ARM / Thumb mode switching with .code 16 and .code 32. 
llvm-svn: 134760
 2011-07-08 22:36:29 +00:00
Evan Cheng 8b2bda09a5 Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. 
llvm-svn: 134590
 2011-07-07 03:55:05 +00:00
Kevin Enderby 6aac575c9f Update MC/ELF/relocation.s with change to X86 PUSH64i8 in r134501. 
llvm-svn: 134511
 2011-07-06 17:55:20 +00:00
Kevin Enderby 6ee1d2bd78 Changed the X86 PUSH64i8 record to use the i64i8imm ParserMatchClass so that a 
push with a small constant produces a 2-byte push.

llvm-svn: 134501
 2011-07-06 17:23:46 +00:00
Eli Friedman 415412e82f Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269. 
llvm-svn: 134424
 2011-07-05 18:21:20 +00:00
Joerg Sonnenberger 91e5662075 Recognize the xstorerng alias for VIA PadLock's xstore instruction. 
llvm-svn: 134126
 2011-06-30 01:38:03 +00:00
Jim Grosbach 76346c3bf7 Asm parser range checking on .<size> <value> directives. 
For example, ".byte 256" would previously assert() when emitting an object
file. Now it generates a diagnostic that the literal value is out of range.

rdar://9686950

llvm-svn: 134069
 2011-06-29 16:05:14 +00:00
Jim Grosbach 16896325a6 ARM Thumb2 asm syntax optional destination operand for binary operators. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867

llvm-svn: 133973
 2011-06-28 00:19:13 +00:00
Jim Grosbach a6f7a1efcc ARM Assembly support for Thumb mov-immediate. 
Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.

llvm-svn: 133966
 2011-06-27 23:54:06 +00:00
Jim Grosbach 89bbfc434a ARM assembler support for ldmfd/stmfd mnemonics. 
llvm-svn: 133936
 2011-06-27 20:32:18 +00:00
Jim Grosbach 29882a75eb ARM assembler support for vpush/vpop. 
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

llvm-svn: 133932
 2011-06-27 20:00:07 +00:00
Jim Grosbach b5ee311602 ARM Assembly syntax support for arithmetic implied dest operand. 
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597

llvm-svn: 133925
 2011-06-27 19:09:15 +00:00
Jim Grosbach 8fbb89ffa4 Move ARM-specific test to ARM directory. 
Hopefully make the x86-target-only Windows bots happy.

llvm-svn: 133856
 2011-06-25 01:53:17 +00:00
Jim Grosbach 045e26166a Testcase for r133818 
llvm-svn: 133823
 2011-06-24 20:59:01 +00:00
Eli Friedman 5c958bb528 Add support for movntil/movntiq mnemonics. Reported on llvmdev. 
llvm-svn: 133759
 2011-06-23 21:07:47 +00:00
Nick Lewycky ef9c497e4c Add support for assembling "movq" when it's correct to do so, while continuing 
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.

llvm-svn: 133565
 2011-06-21 22:45:41 +00:00
Bob Wilson 646dd0f4d1 Revert r133452: "Emit movq for 64-bit register to XMM register moves..." 
This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

llvm-svn: 133524
 2011-06-21 17:35:13 +00:00
Nick Lewycky c7df192279 Emit movq for 64-bit register to XMM register moves, but continue to accept 
movd when assembling.

llvm-svn: 133452
 2011-06-20 18:33:26 +00:00
Hans Wennborg 3fefc65c1d MC: Allow .common as alias for .comm assembler directive. PR10116. 
llvm-svn: 133349
 2011-06-18 13:51:54 +00:00