69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
82ed3be1fb
Fixed a bug in the code to create a dwarf file and directory table entires when
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it is separating the directory part from the basename of the FileName. Noticed
that this:
.file 1 "dir/foo"
when assembled got the two parts switched. Using the Mac OS X dwarfdump tool
it can be seen easily:
% dwarfdump -a a.out
include_directories[ 1] = 'foo'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 dir
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Which should be:
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include_directories[ 1] = 'dir'
Dir Mod Time File Len File Name
---- ---------- ---------- ---------------------------
file_names[ 1] 1 0x00000000 0x00000000 foo
llvm-svn: 143521
2011-11-01 23:39:05 +00:00
69e54a740c
Fix disassembly of some VST1 instructions.
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llvm-svn: 143507
2011-11-01 22:18:13 +00:00
300dcb8e37
Move test to the X86 directory, note the PR number and only run MC once.
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llvm-svn: 143352
2011-10-31 17:23:09 +00:00
40703f4252
More not-crashing NEON disassembly updates for the vld refactoring.
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llvm-svn: 143351
2011-10-31 17:17:32 +00:00
b009a872d7
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
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When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
llvm-svn: 143235
2011-10-28 22:36:30 +00:00
5524ce7d82
Fix illegal disassembly testcase.
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llvm-svn: 143231
2011-10-28 21:45:09 +00:00
dde461c8b1
Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle.
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llvm-svn: 143208
2011-10-28 18:02:13 +00:00
7a49575d7f
Thumb2 ADD/SUB instructions encoding selection outside IT block.
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Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
llvm-svn: 143201
2011-10-28 16:57:07 +00:00
7636f55348
test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction.
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FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
2011-10-28 14:12:30 +00:00
080a499ee0
ARM Allow 'q' registers in VLD/VST vector lists.
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Just treat it as if the constituent D registers where specified.
rdar://10348896
llvm-svn: 143167
2011-10-28 00:06:50 +00:00
f211416dde
Add testcase for r143162.
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llvm-svn: 143163
2011-10-27 22:54:14 +00:00
49e6a0da7e
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and
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not depend on In32BitMode. Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode. rdar://9738584
llvm-svn: 143112
2011-10-27 17:40:41 +00:00
6ed3845530
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
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rdar://10348844
llvm-svn: 143110
2011-10-27 17:33:59 +00:00
ba7f90c7df
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
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rdar://10348584
llvm-svn: 143108
2011-10-27 17:16:55 +00:00
61fdba048f
Thumb2 ldr pc-relative encoding fixes.
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We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
llvm-svn: 143068
2011-10-26 22:22:01 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
295b1e84ce
Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely.
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llvm-svn: 142817
2011-10-24 18:04:29 +00:00
3adec13c3e
Update test for r142801.
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llvm-svn: 142806
2011-10-24 17:26:26 +00:00
b05d9e9bea
Add X86 SARX, SHRX, and SHLX instructions.
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llvm-svn: 142779
2011-10-23 22:18:24 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
e94d277db8
Add X86 MULX instruction for disassembler.
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llvm-svn: 142738
2011-10-23 00:33:32 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
16c8fc5191
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
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llvm-svn: 142626
2011-10-20 22:23:58 +00:00
608c60c773
Fix decoding tests for fixed MSR encodings.
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llvm-svn: 142624
2011-10-20 22:01:48 +00:00
48da0ed477
Fix tests for corrected MSR encodings.
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llvm-svn: 142622
2011-10-20 21:53:19 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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llvm-svn: 142583
2011-10-20 15:04:25 +00:00
3ad44e50b3
Tidy up formatting.
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llvm-svn: 142582
2011-10-20 14:57:47 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
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llvm-svn: 142581
2011-10-20 14:48:50 +00:00
e0d0908356
Fix parsing of a line with only a # in it.
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llvm-svn: 142537
2011-10-19 18:48:52 +00:00
ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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llvm-svn: 142480
2011-10-19 07:48:35 +00:00
43f1d206b9
Tidy up formatting.
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llvm-svn: 142422
2011-10-18 21:09:01 +00:00
1f63e04b2c
Tidy up formatting.
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llvm-svn: 142421
2011-10-18 21:08:16 +00:00
4e5c764b65
Enable more encoded immediate tests.
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llvm-svn: 142415
2011-10-18 20:20:51 +00:00
89f9e1dca4
More vmov lane testcases.
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llvm-svn: 142414
2011-10-18 20:19:48 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
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llvm-svn: 142412
2011-10-18 20:10:47 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142389
2011-10-18 18:27:07 +00:00
40ec1da2ab
Another failing encoding.
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llvm-svn: 142388
2011-10-18 18:23:03 +00:00
32b83a4e16
Fix NEON mul encoding tests. Wrong file contents previously.
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llvm-svn: 142387
2011-10-18 18:14:55 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
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llvm-svn: 142386
2011-10-18 18:12:09 +00:00
d1bc6da657
Remove duplicate test.
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llvm-svn: 142383
2011-10-18 18:05:50 +00:00
b3ecff77cd
Tidy up formatting.
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llvm-svn: 142382
2011-10-18 18:05:16 +00:00
Benjamin Kramer