6f84fed675
Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
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llvm-svn: 144057
2011-11-08 01:43:53 +00:00
f2a9bd4b1e
Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
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Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up.
llvm-svn: 144055
2011-11-08 01:25:24 +00:00
91b56e0390
Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
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llvm-svn: 144052
2011-11-08 00:31:58 +00:00
2197b015c8
Convert to the new EH model.
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llvm-svn: 144049
2011-11-08 00:17:28 +00:00
9b7942a543
Convert tests to the new EH model.
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llvm-svn: 144048
2011-11-08 00:09:27 +00:00
5de1bea5c9
Enable support for returning i1, i8, and i16. Nothing special todo as it's the
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callee's responsibility to sign or zero-extend the return value. The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).
llvm-svn: 144047
2011-11-08 00:03:32 +00:00
2dc40434aa
Added missing newline
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llvm-svn: 144046
2011-11-08 00:03:24 +00:00
a35a5295e0
Revert r144034 while I try to track down a crash.
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llvm-svn: 144044
2011-11-07 23:53:20 +00:00
9279f9efbc
Fix test for Windows as well.
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llvm-svn: 144038
2011-11-07 23:10:43 +00:00
a70e9417fb
Kill and collapse outstanding DomainValues.
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DomainValues that are only used by "don't care" instructions are now
collapsed to the first possible execution domain after all basic blocks
have been processed. This typically means the PS domain on x86.
For example, the vsel_i64 and vsel_double functions in sse2-blend.ll are
completely collapsed to the PS domain instead of containing a mix of
execution domains created by isel.
llvm-svn: 144037
2011-11-07 23:08:21 +00:00
7a4be01ac8
InstCombine now optimizes vector udiv by power of 2 to shifts
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Fixes r8429
llvm-svn: 144036
2011-11-07 23:04:49 +00:00
55a86d32d3
Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
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llvm-svn: 144034
2011-11-07 22:51:10 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
7f076cb6cc
Fix test for Linux.
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llvm-svn: 144003
2011-11-07 20:47:23 +00:00
0241308954
Expand V_SET0 to xorps by default.
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The xorps instruction is smaller than pxor, so prefer that encoding.
The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.
llvm-svn: 143996
2011-11-07 19:15:58 +00:00
a6d409d543
Add AVX2 variable shift instructions and intrinsics.
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llvm-svn: 143915
2011-11-07 08:26:24 +00:00
ff39be0afc
Add AVX2 VPMOVMASK instructions and intrinsics.
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llvm-svn: 143904
2011-11-07 03:20:35 +00:00
e122dcbf4a
Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects.
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llvm-svn: 143902
2011-11-07 02:00:04 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
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llvm-svn: 143895
2011-11-06 23:04:08 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
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llvm-svn: 143861
2011-11-06 06:12:20 +00:00
d0191a53c9
Add support for passing i1, i8, and i16 call parameters. Also, be sure to
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zero-extend the constant integer encoding. Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.
llvm-svn: 143821
2011-11-05 20:16:15 +00:00
c74798d5cf
Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 encoding from the DWARF asm printer.
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As a side effect we now print dwarf ulebs with .ascii directives.
llvm-svn: 143809
2011-11-05 11:52:44 +00:00
8f249600e7
Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes.
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I'm going to wait for any review comments and perform some additional testing before turning this on by default.
llvm-svn: 143750
2011-11-04 23:46:11 +00:00
b9a46e6b83
Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
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llvm-svn: 143682
2011-11-04 06:59:21 +00:00
f3e73ad5da
Add fast-isel support for returning i1, i8, and i16.
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llvm-svn: 143669
2011-11-04 00:50:21 +00:00
198b7ffc11
Reapply r143206, with fixes. Disallow physical register lifetimes
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across calls, and only check for nested dependences on the special
call-sequence-resource register.
llvm-svn: 143660
2011-11-03 21:49:52 +00:00
65ba66c660
Reverted r143600 - selector reference change
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llvm-svn: 143646
2011-11-03 20:47:50 +00:00
b68515c232
fixed global array handling for ptx to use the correct bit widths
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llvm-svn: 143640
2011-11-03 19:24:46 +00:00
0e7cbbabea
Add new X86 AVX2 VBROADCAST instructions.
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llvm-svn: 143612
2011-11-03 07:35:53 +00:00
bf5f4bec1a
Add support for sign-extending non-legal types in SelectSIToFP().
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llvm-svn: 143603
2011-11-03 02:04:59 +00:00
e6173d81ae
Treat objc selector reference globals as invariant so that MachineLICM can hoist them out of loops. Fixes <rdar://problem/6027699>
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llvm-svn: 143600
2011-11-03 00:56:36 +00:00
9929c423a1
Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits.
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llvm-svn: 143582
2011-11-02 22:52:45 +00:00
d1ee7f8cf1
Don't emit a directory entry for the value in DW_AT_comp_dir, that is always
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implied by directory index zero.
llvm-svn: 143570
2011-11-02 20:55:33 +00:00
9cf803c4bf
Add support for comparing integer non-legal types.
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llvm-svn: 143559
2011-11-02 18:08:25 +00:00
a47b05c7f3
More AVX2 instructions and intrinsics.
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llvm-svn: 143536
2011-11-02 06:54:17 +00:00
682b850602
Add a bunch more X86 AVX2 instructions and their corresponding intrinsics.
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llvm-svn: 143529
2011-11-02 04:42:13 +00:00
3f5eccbe7a
Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289.
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llvm-svn: 143498
2011-11-01 21:18:39 +00:00
56ce0932db
Don't fold negative offsets into cp / dp accesses to avoid relocation errors.
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This can happen if the address + addend is less than the start of the cp / dp.
llvm-svn: 143459
2011-11-01 11:31:53 +00:00
37fe7d6641
Combine various XCore tests for floating point intrinsic support into a single test.
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llvm-svn: 143458
2011-11-01 10:51:48 +00:00
8591b6b0ab
Move various XCore tests to FileCheck
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llvm-svn: 143457
2011-11-01 10:41:28 +00:00
fec80c6ad2
Fix operand type for x86 pmadd_ub_sw intrinsic.
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llvm-svn: 143455
2011-11-01 07:25:22 +00:00
9821e75e64
Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsic
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llvm-svn: 143336
2011-10-31 07:16:37 +00:00
242d1f8c73
Test case for X86 FS/GS Base intrinsics
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llvm-svn: 143332
2011-10-31 02:15:47 +00:00
cfcfdf2aab
Begin adding AVX2 instructions. No selection support yet other than intrinsics.
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llvm-svn: 143331
2011-10-31 02:15:10 +00:00
aab6169ef6
Switch new .file directive emission off by default, change llc's flag for it to
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-enable-dwarf-directory.
llvm-svn: 143326
2011-10-31 01:06:02 +00:00
7402ee6ec2
X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in.
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llvm-svn: 143315
2011-10-30 17:31:21 +00:00
9cdb9ffa43
Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector of 8-bit integers, but produces a vector of 16-bit integers.
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llvm-svn: 143313
2011-10-30 17:22:45 +00:00
c602b2c4de
Fix pr11266.
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On x86: (shl V, 1) -> add V,V
Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.
llvm-svn: 143311
2011-10-30 13:24:22 +00:00
1dda6a8ce1
Stabilize the test by specifying an exact cpu target
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llvm-svn: 143307
2011-10-30 08:07:50 +00:00
bf6568b5d6
Add a new DAGCombine optimization for BUILD_VECTOR.
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If all of the inputs are zero/any_extended, create a new simple BV
which can be further optimized by other BV optimizations.
llvm-svn: 143297
2011-10-29 21:23:04 +00:00
Eli Friedman