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1115 Commits

Author SHA1 Message Date
Chad Rosier a476e391f1 Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier c8cfd3a8fb Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Jakob Stoklund Olesen 7ef502f6d1 Delete the 'standard' spiller with used the old spilling framework. 
The current register allocators all use the inline spiller.

llvm-svn: 144477
 2011-11-12 23:29:02 +00:00
Jakob Stoklund Olesen 0eac531bc2 RAGreedy is better about hinting now. 
Or maybe we are just getting lucky.

llvm-svn: 144473
 2011-11-12 22:39:37 +00:00
Jakob Stoklund Olesen 8ec1a92afd Linear scan is going away. 
llvm-svn: 144472
 2011-11-12 22:39:34 +00:00
Jakob Stoklund Olesen 654d60888e XFAIL test that depends on linear scan to remove dead code. 
Filed PR11364 to track the problem.  Should the register allocator
eliminate dead code?

llvm-svn: 144471
 2011-11-12 22:39:30 +00:00
Jakob Stoklund Olesen 4deff7bc1d Switch a few tests off linearscan. 
llvm-svn: 144460
 2011-11-12 19:53:52 +00:00
Eli Friedman 9d448e4a42 Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029. 
llvm-svn: 144438
 2011-11-12 00:35:34 +00:00
Chad Rosier a7ebc5617d Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Chad Rosier ab1a4a2301 Loosen test by using REs. Approved by Devang. 
llvm-svn: 144425
 2011-11-11 23:25:38 +00:00
Andrew Trick 28c1d18434 Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.

llvm-svn: 144409
 2011-11-11 22:18:09 +00:00
Chad Rosier 7ddd63ce4e Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Eli Friedman c4a001478c Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
llvm-svn: 144361
 2011-11-11 03:16:38 +00:00
Chad Rosier 2a3503e061 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Chad Rosier d1762e00e2 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Chad Rosier 3fbd094ad9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Eli Friedman 2d4055b683 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
llvm-svn: 144241
 2011-11-09 23:36:02 +00:00
Eli Friedman 53218b6fcc Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. 
llvm-svn: 144216
 2011-11-09 22:25:12 +00:00
Chad Rosier c22f6518b2 Use REs to remove dependencies on the register allocation order. 
llvm-svn: 144209
 2011-11-09 20:06:13 +00:00
Chad Rosier 595d419427 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Evan Cheng c3770ac687 Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
llvm-svn: 144123
 2011-11-08 21:21:09 +00:00
Lang Hames b85fcd07df Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.

llvm-svn: 144102
 2011-11-08 18:56:23 +00:00
Eli Friedman 6f84fed675 Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
llvm-svn: 144057
 2011-11-08 01:43:53 +00:00
Bill Wendling 9b7942a543 Convert tests to the new EH model. 
llvm-svn: 144048
 2011-11-08 00:09:27 +00:00
Chad Rosier 5de1bea5c9 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Benjamin Kramer 69d57cf9c4 Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Chad Rosier d0191a53c9 Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
 2011-11-05 20:16:15 +00:00
Benjamin Kramer c74798d5cf Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 encoding from the DWARF asm printer. 
As a side effect we now print dwarf ulebs with .ascii directives.

llvm-svn: 143809
 2011-11-05 11:52:44 +00:00
Chad Rosier f3e73ad5da Add fast-isel support for returning i1, i8, and i16. 
llvm-svn: 143669
 2011-11-04 00:50:21 +00:00
Chad Rosier bf5f4bec1a Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Lang Hames 9929c423a1 Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
llvm-svn: 143582
 2011-11-02 22:52:45 +00:00
Chad Rosier 9cf803c4bf Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Nick Lewycky cc64ae140d Always use the string pool, even when it makes the .o larger. This may help 
tools that read the debug info in the .o files by making the DIE sizes more
consistent.

llvm-svn: 143186
 2011-10-28 05:29:47 +00:00
Jakob Stoklund Olesen e5a6adceac Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

llvm-svn: 143160
 2011-10-27 22:39:16 +00:00
Evan Cheng f4807a19e8 Avoid partial CPSR dependency from loop backedges. rdar://10357570 
llvm-svn: 143145
 2011-10-27 21:21:05 +00:00
Nick Lewycky d59c0cac6c Teach our Dwarf emission to use the string pool. 
llvm-svn: 143097
 2011-10-27 06:44:11 +00:00
Chad Rosier d24e7e1d9b A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Lang Hames c47e283430 Make sure short memsets on ARM lower to stores, even when optimizing for size. 
llvm-svn: 143055
 2011-10-26 20:56:52 +00:00
Jim Grosbach 25d4707c4d Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. 
llvm-svn: 143034
 2011-10-26 17:28:15 +00:00
James Molloy dd9137aa56 Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance. 
llvm-svn: 143023
 2011-10-26 08:53:19 +00:00
Evan Cheng 043c9d3f7a Revert part of r142530. The patch potentially hurts performance especially 
on Darwin platforms where -Os means optimize for size without hurting
performance.

llvm-svn: 143002
 2011-10-26 01:17:44 +00:00
Eli Friedman a5e244c08d Don't crash on variable insertelement on ARM. PR10258. 
llvm-svn: 142871
 2011-10-24 23:08:52 +00:00
Bill Wendling 57e3aaad89 Check the visibility of the global variable before placing it into the stubs 
table. A hidden variable could potentially end up in both lists.
<rdar://problem/10336715>

llvm-svn: 142869
 2011-10-24 23:05:43 +00:00
Chad Rosier add38c12b8 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( 
llvm-svn: 142557
 2011-10-20 00:07:12 +00:00
James Molloy 2d768fd379 Use literal pool loads instead of MOVW/MOVT for materializing global addresses when optimizing for size. 
On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is
codesize including literal pools.

The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there
is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries.

Fixes PR11087.

llvm-svn: 142530
 2011-10-19 14:11:07 +00:00
Bob Wilson 9258b76d8d Fix incorrect check for sign-extended constant BUILD_VECTOR. 
<rdar://problem/10298332>

llvm-svn: 142371
 2011-10-18 17:34:51 +00:00
Bob Wilson 681561901d Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. 
svn r139159 caused SelectionDAG::getConstant() to promote BUILD_VECTOR operands
with illegal types, even before type legalization.  For this testcase, that led
to one BUILD_VECTOR with i16 operands and another with promoted i32 operands,
which triggered the assertion.

llvm-svn: 142370
 2011-10-18 17:34:47 +00:00
Chad Rosier 0ffe593a16 Add support for dynamic stack realignment when in thumb1 mode. 
rdar://10288916

llvm-svn: 142337
 2011-10-18 05:28:00 +00:00
Nadav Rotem d2c72d6d03 Add CHECKs and document PR11158. 
llvm-svn: 142240
 2011-10-17 20:23:23 +00:00
Nadav Rotem 486ff59a9f Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00