Commit Graph

527 Commits

Author SHA1 Message Date
Reed Kotler 7bff8f1d7a set register class properly for mips16 here
llvm-svn: 170669
2012-12-20 06:06:35 +00:00
Reed Kotler 92fc33bc97 This assert is overly restrictive and does not work for mips16.
llvm-svn: 170667
2012-12-20 05:09:15 +00:00
Reed Kotler 5fdeb21249 This code implements most of mips16 hardfloat as it is done by gcc.
In this case, essentially it is soft float with different library routines.
The next step will be to make this fully interoperational with mips32 floating
point and that requires creating stubs for functions with signatures that
contain floating point types.

I have a more sophisticated design for mips16 hardfloat which I hope to
implement at a later time that directly does floating point without the need
for function calls.

The mips16 encoding has no floating point instructions so one needs to
switch to mips32 mode to execute floating point instructions.

llvm-svn: 170259
2012-12-15 00:20:05 +00:00
Patrik Hagglund 5e6c361bc0 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.

llvm-svn: 170104
2012-12-13 06:34:11 +00:00
Akira Hatanaka cf9a61b6ee [mips] Do not copy GOT address to register $gp if the function being called has
internal linkage.

llvm-svn: 170092
2012-12-13 03:17:29 +00:00
Evan Cheng 962711ee71 Sorry about the churn. One more change to getOptimalMemOpType() hook. Did I
mention the inline memcpy / memset expansion code is a mess?

This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset.
The first indicates whether it is expanding a memset or a memcpy / memmove.
The later is whether the memset is a memset of zero. It's totally possible
(likely even) that targets may want to do different things for memcpy and
memset of zero.

llvm-svn: 169959
2012-12-12 02:34:41 +00:00
Evan Cheng c3d1aca657 - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.
Also added more comments to explain why it is generally ok to return true.
- Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to
be true for loaded source (memcpy) or zero constants (memset). The poor name
choice is probably some kind of legacy issue.

llvm-svn: 169954
2012-12-12 01:32:07 +00:00
Patrik Hagglund e98b7a0389 Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
llvm-svn: 169854
2012-12-11 11:14:33 +00:00
Patrik Hagglund 3708e548f8 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

llvm-svn: 169837
2012-12-11 09:10:33 +00:00
Evan Cheng 79e2ca90bc Some enhancements for memcpy / memset inline expansion.
1. Teach it to use overlapping unaligned load / store to copy / set the trailing
   bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies.
2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g.
   x86 and ARM.
3. When memcpy from a constant string, do *not* replace the load with a constant
   if it's not possible to materialize an integer immediate with a single
   instruction (required a new target hook: TLI.isIntImmLegal()).
4. Use unaligned load / stores more aggressively if target hooks indicates they
   are "fast".
5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8.
   Also increase the threshold to something reasonable (8 for memset, 4 pairs
   for memcpy).

This significantly improves Dhrystone, up to 50% on ARM iOS devices.

rdar://12760078

llvm-svn: 169791
2012-12-10 23:21:26 +00:00
Akira Hatanaka efdce0fb09 [mips] Delete nodes and instructions for dynamic alloca that are no longer in
use.

llvm-svn: 169580
2012-12-07 03:10:18 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Akira Hatanaka bb6e74a2f1 [mips] Generate big GOT code.
llvm-svn: 168460
2012-11-21 20:40:38 +00:00
Akira Hatanaka 56d5f1bca5 [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper
functions added in r168456.

llvm-svn: 168458
2012-11-21 20:30:40 +00:00
Akira Hatanaka fd04ad4261 [mips] Add helper functions that create nodes for computing address.
llvm-svn: 168456
2012-11-21 20:26:38 +00:00
Akira Hatanaka 59f299f28e [mips] Add command line option "-mxgot".
llvm-svn: 168455
2012-11-21 20:21:11 +00:00
Akira Hatanaka dbe41ad18c [mips] When a node which loads from a GOT is created, pass a MachinePointerInfo
referring to a GOT entry.

llvm-svn: 168453
2012-11-21 20:16:34 +00:00
Akira Hatanaka ef83919b4c Initial implementation of MipsTargetLowering::isLegalAddressingMode.
llvm-svn: 168230
2012-11-17 00:25:41 +00:00
Akira Hatanaka 28e02ec8c1 [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.
Patch by Sasa Stankovic.

llvm-svn: 167548
2012-11-07 19:10:58 +00:00
Akira Hatanaka 40f2d30987 Delete MipsFunctionInfo::NextStackOffset. No functionality change intended.
llvm-svn: 167546
2012-11-07 19:04:26 +00:00
Akira Hatanaka 719df2874c [mips] Add member field MipsFunctionInfo::IncomingArgSize which holds the size
of the incoming argument area.

llvm-svn: 167312
2012-11-02 21:03:58 +00:00
Akira Hatanaka 9c962c02e4 [mips] Allow tail-call optimization for vararg functions and functions which
use the caller's stack.

llvm-svn: 167048
2012-10-30 20:16:31 +00:00
Akira Hatanaka 4866fe14e2 Add code for saving formal argument information to MipsFunctionInfo. This
information will be used by IsEligibleForTailCallOptimization to determine
whether a call can be tail-call optimized.

llvm-svn: 167043
2012-10-30 19:37:25 +00:00
Akira Hatanaka 6233cf565f Add definition of function MipsTargetLowering::passArgOnStack which emits nodes
for passing a function call argument on a stack.

llvm-svn: 167041
2012-10-30 19:23:25 +00:00
Akira Hatanaka 8e50aba5f9 Do not do tail-call optimization if target is mips16.
llvm-svn: 167039
2012-10-30 19:07:58 +00:00
Reed Kotler aebb8b034c Expand all atomic ops for mips16.
llvm-svn: 166935
2012-10-29 16:16:54 +00:00
Akira Hatanaka 6a124a84dc [mips] Do not tail-call optimize vararg functions or functions with byval
arguments.

This is rather conservative and should be fixed later to be more aggressive.

llvm-svn: 166851
2012-10-27 00:56:56 +00:00
Akira Hatanaka 2c07f1f140 [mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in the
previous iteration.

llvm-svn: 166850
2012-10-27 00:44:39 +00:00
Akira Hatanaka ac8c669985 Use the methods and classes that were added to simplify LowerCall and
LowerFormalArguments in MipsTargetLowering.

No functionality change intended.

llvm-svn: 166846
2012-10-27 00:29:43 +00:00
Akira Hatanaka 2a13402a66 Add method MipsTargetLowering::writeVarArgRegs which copies argument registers
of vararg functions back to the stack.

llvm-svn: 166844
2012-10-27 00:21:13 +00:00
Akira Hatanaka 35f55b1622 Add method MipsTargetLowering::passByValArg.
This method emits nodes for passing byval arguments in registers and stack.
This has the same functionality as existing functions PassByValArg64 and
WriteByValArg which will be deleted later.

llvm-svn: 166843
2012-10-27 00:16:36 +00:00
Akira Hatanaka 25dad19f0e Add method MipsTargetLowering::copyByValRegs.
This method copies byval arguments passed in registers onto the stack and has
the same functionality as existing functions CopyMips64ByValRegs and
ReadByValArg which will be deleted later.

llvm-svn: 166841
2012-10-27 00:10:18 +00:00
Akira Hatanaka 4a3711d077 Add class MipsCC which provides methods used to analyze formal and call
arguments and inquire about calling convention information.

llvm-svn: 166840
2012-10-26 23:56:38 +00:00
Akira Hatanaka e485c65642 Delete MipsFunctionInfo::InArgFIRange.
llvm-svn: 166837
2012-10-26 23:49:51 +00:00
Akira Hatanaka 868b3a333b [mips] Make sure sret argument is returned in register V0.
llvm-svn: 166539
2012-10-24 02:10:54 +00:00
Akira Hatanaka 0c7d131a7b [mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
llvm-svn: 166344
2012-10-19 22:11:40 +00:00
Akira Hatanaka 90131ac26c [mips] Add code to do tail call optimization.
Currently, it is enabled only if option "enable-mips-tail-calls" is given and
all of the callee's arguments are passed in registers.

llvm-svn: 166342
2012-10-19 21:47:33 +00:00
Akira Hatanaka c046243488 [mips] Delete MipsFunctionInfo::MaxCallFrameSize which is no longer used.
llvm-svn: 166339
2012-10-19 21:18:38 +00:00
Akira Hatanaka 91318df0cc Add node and enum for mips tail call.
llvm-svn: 166318
2012-10-19 20:59:39 +00:00
Akira Hatanaka 9c8dcfc73a Implement MipsTargetLowering::CanLowerReturn.
Patch by Sasa Stankovic. 

llvm-svn: 165585
2012-10-10 01:27:09 +00:00
Reed Kotler 240322140e Patch for integer multiply, signed/unsigned, long/long long.
llvm-svn: 165322
2012-10-05 18:27:54 +00:00
Akira Hatanaka e4bd054f98 MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
llvm-svn: 164751
2012-09-27 02:15:57 +00:00
Akira Hatanaka 9061a46443 MIPS DSP: all the remaining instructions which read or write accumulators.
llvm-svn: 164750
2012-09-27 02:11:20 +00:00
Akira Hatanaka 1babeaa44c MIPS DSP: add support for extract-word instructions.
llvm-svn: 164749
2012-09-27 02:05:42 +00:00
Akira Hatanaka fabb8cf421 Add MIPS DSP register classes. Set actions of DSP vector operations and override
TargetLowering's callback functions.

llvm-svn: 164431
2012-09-21 23:58:31 +00:00
Akira Hatanaka 233ac53a3f SelectionDAG node enums for MIPS DSP nodes.
llvm-svn: 164430
2012-09-21 23:52:47 +00:00
Akira Hatanaka 189d0adde9 Handled unaligned load/stores properly in Mips16
Patch by Reed Kotler.

llvm-svn: 163956
2012-09-15 01:02:03 +00:00
Akira Hatanaka 92a96e1da4 Misc.
1. Remove RA from list of allocatable registers
2. Enable d,y,r constraint inline assembly instructions

Patch by Reed Kotler.

llvm-svn: 163753
2012-09-12 23:27:55 +00:00
Michael Liao abb87d4857 Fix PR11985
- BlockAddress has no support of BA + offset form and there is no way to
  propagate that offset into machine operand;
- Add BA + offset support and a new interface 'getTargetBlockAddress' to
  simplify target block address forming;
- All targets are modified to use new interface and X86 backend is enhanced to
  support BA + offset addressing.

llvm-svn: 163743
2012-09-12 21:43:09 +00:00
Roman Divacky ad06cee239 Stop casting away const qualifier needlessly.
llvm-svn: 163258
2012-09-05 22:26:57 +00:00
Akira Hatanaka ad4950258b Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.

llvm-svn: 162340
2012-08-22 03:18:13 +00:00
Akira Hatanaka 33a25af5a8 Expand DYNAMIC_STACKALLOC nodes rather than doing custom-lowering.
The frame object which points to the dynamically allocated area will not be
needed after changes are made to cease reserving call frames.

llvm-svn: 161076
2012-07-31 20:54:48 +00:00
Akira Hatanaka beda2241a4 When store nodes or memcpy nodes are created to copy the function call
arguments to the stack in MipsISelLowering::LowerCall, use stack pointer and
integer offset operands rather than frame object operands.

llvm-svn: 161068
2012-07-31 18:46:41 +00:00
Akira Hatanaka 4ce7c4060d Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063
2012-07-31 18:16:49 +00:00
Akira Hatanaka 97ba7696f8 Pass the correct call frame size to callseq_start node. This is needed to
replace uses of function getMaxCallFrameSize defined in MipsFunctionInfo with
the one MachineFrameInfo has.

llvm-svn: 160841
2012-07-26 23:27:01 +00:00
Akira Hatanaka 64626fc20f Fix call setup for PIC.
Patch by Reed Kotler.

llvm-svn: 160774
2012-07-26 02:24:43 +00:00
Akira Hatanaka 26e9ecb7a3 Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.

Patch by Reed Kotler.

llvm-svn: 160651
2012-07-23 23:45:54 +00:00
Akira Hatanaka b49c68a65d Revert accidental commit.
llvm-svn: 160598
2012-07-21 02:20:33 +00:00
Akira Hatanaka f73e362758 Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind.
Test case will be added later when long branch patch is checked in.

llvm-svn: 160597
2012-07-21 02:15:19 +00:00
Akira Hatanaka 24cf4e36e5 Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.
llvm-svn: 160064
2012-07-11 19:32:27 +00:00
Akira Hatanaka 878ad8b28d Lower RETURNADDR node in Mips backend.
Patch by Sasa Stankovic.

llvm-svn: 160031
2012-07-11 00:53:32 +00:00
Akira Hatanaka efff7b763b Make register Mips::RA allocatable if not in mips16 mode.
llvm-svn: 159971
2012-07-10 00:19:06 +00:00
Jack Carter b353094f27 mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159625
2012-07-02 23:35:23 +00:00
Eric Christopher dfc3e68c40 Revert " mips32 long long register inline asm constraint support." as
it appears to be breaking the bots.

This reverts commit 1b055ce320fa13f6f1ac81670d11b45e01f79876.

llvm-svn: 159619
2012-07-02 23:22:25 +00:00
Jack Carter 5c1a01a625 mips32 long long register inline asm constraint support.
inlineasm-cnstrnt-bad-r-1.ll is NOT supposed to fail, so it was removed.    This resulted in the removal of a negative test (inlineasm-cnstrnt-bad-r-1.ll)
    

llvm-svn: 159610
2012-07-02 22:39:45 +00:00
Akira Hatanaka 5fd22485a3 Fix coding style violations. Remove white spaces and tabs.
llvm-svn: 158471
2012-06-14 21:10:56 +00:00
Akira Hatanaka df5205ef3d Implement a DAGCombine in MipsISelLowering.cpp which transforms the following
pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419
2012-06-13 20:33:18 +00:00
Akira Hatanaka 1daf8c2a16 Set a higher value for maxStoresPerMemcpy in MipsISelLowering.cpp.
llvm-svn: 158414
2012-06-13 19:33:32 +00:00
Akira Hatanaka 9586618c58 Simplify CreateLoadLR and CreateStoreLR in MipsISelLowering.cpp.
llvm-svn: 158413
2012-06-13 19:06:08 +00:00
Akira Hatanaka f0273603f5 Implement fastcc calling convention for MIPS.
llvm-svn: 158410
2012-06-13 18:06:00 +00:00
Akira Hatanaka 6734685f21 Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node is
inserted after the shift-left-logical node.

llvm-svn: 157937
2012-06-04 17:46:29 +00:00
Hans Wennborg 245917b536 MIPS TLS: use the model selected by TargetMachine::getTLSModel().
This was mostly done already in r156162, but I missed one place.

llvm-svn: 157929
2012-06-04 14:02:08 +00:00
Chris Lattner 58268c23ac remove an unused variable.
llvm-svn: 157872
2012-06-02 01:03:42 +00:00
Akira Hatanaka 019e592f75 Set operation actions for load/store nodes in the Mips backend.
llvm-svn: 157866
2012-06-02 00:04:42 +00:00
Akira Hatanaka 8f1db778a4 Define functions MipsTargetLowering::LowerLOAD and LowerSTORE which
custom-lower unaligned load and store nodes.

llvm-svn: 157864
2012-06-02 00:03:49 +00:00
Akira Hatanaka b9ebf8d644 Define Mips specific unaligned load/store nodes.
llvm-svn: 157863
2012-06-02 00:03:12 +00:00
Akira Hatanaka 4e76bf8282 Expand unaligned i16 loads/stores for the Mips backend.
This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.

llvm-svn: 157862
2012-06-02 00:02:45 +00:00
Akira Hatanaka bff8e31d3c Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.

Patch by Reed Kotler.

llvm-svn: 157730
2012-05-31 02:59:44 +00:00
Justin Holewinski aa58397b3c Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values.  This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.

NV_CONTRIB

llvm-svn: 157479
2012-05-25 16:35:28 +00:00
Akira Hatanaka f542ebd958 Make the following changes in MipsISelLowering.cpp:
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.

llvm-svn: 156692
2012-05-12 03:19:04 +00:00
Akira Hatanaka 0a8ab718cb Expand 64-bit shifts if target ABI is O32.
llvm-svn: 156457
2012-05-09 00:55:21 +00:00
Eric Christopher 0d8c15d20f Add support for the 'x' constraint.
Patch by Jack Carter.

llvm-svn: 156295
2012-05-07 06:25:19 +00:00
Eric Christopher 9c492e6ebf Add support for the 'l' constraint.
Patch by Jack Carter.

llvm-svn: 156294
2012-05-07 06:25:15 +00:00
Eric Christopher e3c494de82 Add support for the 'c' constraint.
Patch by Jack Carter.

llvm-svn: 156293
2012-05-07 06:25:10 +00:00
Eric Christopher c18ae4a3b1 Add support for the 'P' constraint.
Patch by Jack Carter.

llvm-svn: 156292
2012-05-07 06:25:02 +00:00
Eric Christopher 470578a91b Add support for the 'O' constraint.
Patch by Jack Carter.

llvm-svn: 156285
2012-05-07 05:46:48 +00:00
Eric Christopher e07aa430b8 Add support for the 'N' inline asm constraint.
Patch by Jack Carter.

llvm-svn: 156284
2012-05-07 05:46:43 +00:00
Eric Christopher 1109b3406d Add support for the 'L' inline asm constraint.
Patch by Jack Carter.

llvm-svn: 156283
2012-05-07 05:46:37 +00:00
Eric Christopher 3ff88a05b7 Add support for the inline asm constraint 'K'.
llvm-svn: 156282
2012-05-07 05:46:29 +00:00
Eric Christopher 7201e1b4b9 Support the 'J' constraint.
Patch by Jack Carter.

llvm-svn: 156280
2012-05-07 03:13:42 +00:00
Eric Christopher 1d6c89eea1 Add support for the 'I' inline asm constraint. Also add tests
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
2012-05-07 03:13:32 +00:00
Eric Christopher 58daf04681 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
Patch by Jack Carter.

llvm-svn: 156278
2012-05-07 03:13:22 +00:00
Eric Christopher cfcd77b0bc When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
2012-05-07 03:13:16 +00:00
Hans Wennborg aea412008e Make ARM and Mips use TargetMachine::getTLSModel()
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
2012-05-04 09:40:39 +00:00
NAKAMURA Takumi e30303fa86 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
2012-04-21 15:31:45 +00:00
Craig Topper c7242e054d Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
llvm-svn: 155188
2012-04-20 07:30:17 +00:00
Akira Hatanaka 47ad674f67 Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
otherwise expand FNEG during legalization.

llvm-svn: 154546
2012-04-11 22:59:08 +00:00
Akira Hatanaka 7f4c9d1429 Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545
2012-04-11 22:49:04 +00:00
Akira Hatanaka 4f5c8421b3 Fix bugs in lowering of FCOPYSIGN nodes.
- FCOPYSIGN nodes that have operands of different types were not handled.
- Different code was generated depending on the endianness of the target.

Additionally, code is added that emits INS and EXT instructions, if they are
supported by target (they are R2 instructions).

llvm-svn: 154540
2012-04-11 22:13:04 +00:00
Akira Hatanaka 121342fcc2 Reapply 154038 without the failing test.
llvm-svn: 154062
2012-04-04 22:16:36 +00:00
Owen Anderson 4743c6e159 Revert r154038. It was causing make check failures.
llvm-svn: 154054
2012-04-04 21:18:58 +00:00
Akira Hatanaka 9705c865d9 Fix LowerGlobalAddress to produce instructions with the correct relocation
types for N32 ABI. Add new test case and update existing ones.

llvm-svn: 154038
2012-04-04 19:02:38 +00:00
Akira Hatanaka 591ecdd7c1 Fix LowerJumpTable to produce instructions with the correct relocation
types for N32 ABI. Test case will be updated after the patch that fixes
TargetLowering::getPICJumpTableRelocBase is checked in.

llvm-svn: 154036
2012-04-04 18:31:32 +00:00
Akira Hatanaka b3a2b8c199 Fix LowerConstantPool to produce instructions with the correct relocation
types for N32 ABI and update test case.

llvm-svn: 154034
2012-04-04 18:26:12 +00:00
Akira Hatanaka aeff24e424 Fix LowerBlockAddress to produce instructions with the correct relocation
types for N32 ABI and update test case.

llvm-svn: 154031
2012-04-04 18:22:53 +00:00
Akira Hatanaka 0603ad8c65 Expand FREM.
llvm-svn: 153671
2012-03-29 18:43:11 +00:00
Akira Hatanaka 8a7633c74e Pass the llvm IR pointer value and offset to the constructor of
MachinePointerInfo when getStore is called to create a node that stores an
argument passed in register to the stack. Without this change, the post RA 
scheduler will fail to discover the dependencies between the stores
instructions and the instructions that load from a structure passed by value. 

The link to the related discussion is here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html

llvm-svn: 153499
2012-03-27 03:13:56 +00:00
Akira Hatanaka 769f69f9b6 Fix bug in LowerConstantPool.
llvm-svn: 153498
2012-03-27 02:55:31 +00:00
Craig Topper b25fda95f6 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
Craig Topper bef78fc2ee Convert more static tables of registers used by calling convention to uint16_t to reduce space.
llvm-svn: 152538
2012-03-11 07:57:25 +00:00
Akira Hatanaka da00aa80b6 Do not custom lower i64 nodes if i64 is not a legal type. Move lines that set
operation action of nodes.

llvm-svn: 152452
2012-03-10 00:03:50 +00:00
Akira Hatanaka b7f78592e2 Lower SETCC nodes during legalization. Previously, it was lowered in DAG combine pass.
llvm-svn: 152450
2012-03-09 23:46:03 +00:00
Akira Hatanaka 5e152182a4 Invoke setTargetDAGCombine for SELECT.
llvm-svn: 152290
2012-03-08 03:26:37 +00:00
Akira Hatanaka 7dd7c08419 Swap the operands of a select node if the false (the second) operand is 0.
For example, this pattern 
(select (setcc lhs, rhs, cc), true, 0)
is transformed to this one:
(select (setcc lhs, rhs, inverse(cc)), 0, true)

This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to
replace 0 with $zero.

llvm-svn: 152285
2012-03-08 02:14:24 +00:00
Akira Hatanaka 956dd2261e Set minimum function alignment to 3 if target is Mips64.
llvm-svn: 152282
2012-03-08 01:59:33 +00:00
Akira Hatanaka 5350c24509 Changes for migrating to using register mask operands.
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
Akira Hatanaka 6bbe1f0d10 Fix bugs which were introduced when support for base+index floating point loads
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
2012-03-01 22:12:30 +00:00
Evan Cheng 65f9d19c4f Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
Daniel Dunbar ee7b899343 Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
Evan Cheng 87c7b09d8d Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
2012-02-28 06:42:03 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode
load and store instructions.

llvm-svn: 151611
2012-02-28 02:55:02 +00:00
Akira Hatanaka b049aef2d1 Add an option to use a virtual register as the global base register instead of
reserving a physical register ($gp or $28) for that purpose.

This will completely eliminate loads that restore the value of $gp after every
function call, if the register allocator assigns a callee-saved register, or
eliminate unnecessary loads if it assigns a temporary register. 

example:

.cpload $25       // set $gp.
...
.cprestore 16     // store $gp to stack slot 16($sp).
...
jalr $25          // function call. clobbers $gp.
lw $gp, 16($sp)   // not emitted if callee-saved reg is chosen.
...
lw $2, 4($gp)
...
jalr $25          // function call.
lw $gp, 16($sp)   // not emitted if $gp is not live after this instruction.
...

llvm-svn: 151402
2012-02-24 22:34:47 +00:00
Craig Topper 760b134ffa Make all pointers to TargetRegisterClass const since they are all pointers to static data that should not be modified.
llvm-svn: 151134
2012-02-22 05:59:10 +00:00
Jia Liu 9f6101191b remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.
llvm-svn: 150805
2012-02-17 08:55:11 +00:00
Akira Hatanaka d608bac682 Do not promote i32 arguments to i64. This was causing unnecessary sign extension
instructions to be emitted.

llvm-svn: 150782
2012-02-17 02:20:26 +00:00
Jia Liu dd6c1cd4e8 add Emacs tag and fix some comment error in file headers
llvm-svn: 150775
2012-02-17 01:23:50 +00:00
Craig Topper e55c556a24 Convert assert(0) to llvm_unreachable
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
Akira Hatanaka f0b08445f6 Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is
needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668
2012-02-03 04:33:00 +00:00
Akira Hatanaka 961883c1cf Set the correct stack pointer register.
llvm-svn: 149585
2012-02-02 03:17:04 +00:00
Akira Hatanaka f029537e68 Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer and
selector registers.
 

llvm-svn: 149584
2012-02-02 03:13:40 +00:00
Akira Hatanaka d7970f9e4b Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,
which is what N32/64 does.

llvm-svn: 148875
2012-01-24 23:18:43 +00:00
Akira Hatanaka 7e6c195c11 Pass CCState by reference.
llvm-svn: 148871
2012-01-24 22:07:36 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Akira Hatanaka aac3e06bf7 Enable -soft-float for MIPS.
llvm-svn: 147541
2012-01-04 19:29:11 +00:00
Akira Hatanaka c669d7a6db Have getRegForInlineAsmConstraint return the correct register class when target
is Mips64.

llvm-svn: 147516
2012-01-04 02:45:01 +00:00
Akira Hatanaka 1d8efaba7e Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
case for DCLO and DCLZ.

llvm-svn: 147022
2011-12-21 00:20:27 +00:00
Akira Hatanaka 410ce9cb44 Expand 64-bit CTPOP and CTTZ.
llvm-svn: 147021
2011-12-21 00:14:05 +00:00
Akira Hatanaka 91c052c4d8 Expand 64-bit atomic load and store.
llvm-svn: 147019
2011-12-21 00:02:58 +00:00
Akira Hatanaka 4706ac9715 Add definition of DSBH (Double Swap Bytes within Halfwords) and
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
2011-12-20 23:56:43 +00:00
Akira Hatanaka 79aed157e7 64-bit uint-fp conversion nodes are expanded.
llvm-svn: 147014
2011-12-20 23:40:56 +00:00
Akira Hatanaka 2bb8d068f5 Enable custom lowering DYNAMIC_STACKALLOC nodes.
llvm-svn: 147013
2011-12-20 23:35:46 +00:00
Akira Hatanaka 8e2c02e2d6 Set the correct stack pointer register that should be saved or restored.
llvm-svn: 147012
2011-12-20 23:28:36 +00:00
Akira Hatanaka 9e1d369e3c Tidy up. Simplify logic. No functional change intended.
llvm-svn: 146896
2011-12-19 19:52:25 +00:00
Akira Hatanaka bff84e1914 Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572
2011-12-14 18:26:41 +00:00
Chandler Carruth 637cc6a8aa Initial CodeGen support for CTTZ/CTLZ where a zero input produces an
undefined result. This adds new ISD nodes for the new semantics,
selecting them when the LLVM intrinsic indicates that the undef behavior
is desired. The new nodes expand trivially to the old nodes, so targets
don't actually need to do anything to support these new nodes besides
indicating that they should be expanded. I've done this for all the
operand types that I could figure out for all the targets. Owners of
various targets, please review and let me know if any of these are
incorrect.

Note that the expand behavior is *conservatively correct*, and exactly
matches LLVM's current behavior with these operations. Ideally this
patch will not change behavior in any way. For example the regtest suite
finds the exact same instruction sequences coming out of the code
generator. That's why there are no new tests here -- all of this is
being exercised by the existing test suite.

Thanks to Duncan Sands for reviewing the various bits of this patch and
helping me get the wrinkles ironed out with expanding for each target.
Also thanks to Chris for clarifying through all the discussions that
this is indeed the approach he was looking for. That said, there are
likely still rough spots. Further review much appreciated.

llvm-svn: 146466
2011-12-13 01:56:10 +00:00
Akira Hatanaka faa88c0add Fix indentation.
llvm-svn: 146431
2011-12-12 22:38:19 +00:00
Benjamin Kramer 64ba50a972 Mips: Don't create a dangling IR function just to get the address of a symbol.
llvm-svn: 146340
2011-12-11 12:21:34 +00:00
Akira Hatanaka 5ee8464e48 Rename WrapperPIC. It is now used for both pic and static.
llvm-svn: 146232
2011-12-09 01:53:17 +00:00
Akira Hatanaka 8e16aac534 jalr should use t9 ($25) for indirect calls regardless of the relocation model
specified.

llvm-svn: 146229
2011-12-09 01:45:12 +00:00