Jim Grosbach
7cfd32a006
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
...
llvm-svn: 136267
2011-07-27 21:21:59 +00:00
Jim Grosbach
3f45383ef5
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
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llvm-svn: 136266
2011-07-27 21:20:45 +00:00
Jim Grosbach
03f56d9de6
ARM parsing and encoding of SBFX and UBFX.
...
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
llvm-svn: 136264
2011-07-27 21:09:25 +00:00
Jim Grosbach
36ce7492a6
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
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llvm-svn: 136261
2011-07-27 20:43:44 +00:00
Jim Grosbach
542333ea05
ARM assembly parsing and encoding tests for TST instruction.
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llvm-svn: 136260
2011-07-27 20:38:58 +00:00
Jim Grosbach
f176e1addb
ARM assembly parsing and encoding tests for TEQ instruction.
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llvm-svn: 136259
2011-07-27 20:37:36 +00:00
Jim Grosbach
833b9d3353
ARM assembly parsing and encoding for extend instructions.
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Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
llvm-svn: 136252
2011-07-27 20:15:40 +00:00
Jim Grosbach
4e895470bd
ARM parsing and encoding tests for load/store exclusive instructions.
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llvm-svn: 136105
2011-07-26 18:07:21 +00:00
Jim Grosbach
15e8d74231
ARM assembly parsing and encoding for SWP[B] instructions.
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llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach
f16378479b
ARM parsing and encoding for SVC instruction.
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llvm-svn: 136090
2011-07-26 16:24:27 +00:00
Jim Grosbach
2c374c4fb6
ARM assembly parsing and encoding tests for SUB instruction.
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llvm-svn: 136089
2011-07-26 15:44:05 +00:00
Jim Grosbach
dc45f00cf5
Update ARM STM tests. Fix check: prefix for diagnostic tests.
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llvm-svn: 136088
2011-07-26 15:41:22 +00:00
Jim Grosbach
9becc53e32
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
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llvm-svn: 136013
2011-07-25 23:32:14 +00:00
Jim Grosbach
475c6dbef6
ARM assembly parsing and encoding for SSAT16 instruction.
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llvm-svn: 136006
2011-07-25 23:09:14 +00:00
Jim Grosbach
3a9cbeed73
ARM assembly parsing and encoding for SSAT instruction.
...
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
llvm-svn: 135990
2011-07-25 22:20:28 +00:00
Jim Grosbach
d69b3423a8
Add FIXME
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llvm-svn: 135819
2011-07-22 22:15:38 +00:00
Jim Grosbach
bc5d709ad9
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
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llvm-svn: 135818
2011-07-22 22:13:00 +00:00
Jim Grosbach
e7e1e163db
ARM assembly parsing and encoding updates.
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Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
llvm-svn: 135817
2011-07-22 22:06:05 +00:00
Jim Grosbach
999afadffa
ARM assembly parsing and encoding tests.
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Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
llvm-svn: 135810
2011-07-22 21:34:56 +00:00
Jim Grosbach
5b84e16503
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
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llvm-svn: 135800
2011-07-22 20:51:24 +00:00
Jim Grosbach
e2220221a2
ARM assembly parsing and encoding tests.
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Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
llvm-svn: 135798
2011-07-22 20:30:40 +00:00
Jim Grosbach
8dfcc0bb92
ARM assembly parsing and encoding of SMLAL instruction.
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Fix parsing of carry-setting variant SMLALS and add tests.
llvm-svn: 135797
2011-07-22 20:18:21 +00:00
Jim Grosbach
d7c8c35301
ARM encoding and assembly parsing of SMLAD{X} instructions.
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Fix encoding of destination register. Add tests.
llvm-svn: 135796
2011-07-22 20:11:20 +00:00
Jim Grosbach
0b28f0cca2
ARM testcases for assembly parsing and encoding SMLA* instructions.
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llvm-svn: 135795
2011-07-22 20:01:34 +00:00
Jim Grosbach
d1f8bde10f
ARM assembly parsing and encoding for SMC instruction.
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llvm-svn: 135782
2011-07-22 18:13:31 +00:00
Jim Grosbach
24ace20824
ARM encoding and assembly parsing tests.
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Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
llvm-svn: 135780
2011-07-22 18:04:48 +00:00
Jim Grosbach
0a547701a4
ARM assembly parsing and encoding for SETEND instruction.
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Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Jim Grosbach
4535b9194a
ARM assembly parsing and encoding tests for SEL instruction.
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llvm-svn: 135772
2011-07-22 16:59:33 +00:00
Jim Grosbach
3354674b48
ARM parsing and encoding tests for SBC instruction.
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llvm-svn: 135718
2011-07-21 23:03:59 +00:00
Jim Grosbach
8dbf59d041
ARM testcases for SADD/SASX parsing and encoding.
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llvm-svn: 135715
2011-07-21 23:00:49 +00:00
Jim Grosbach
2a0320c877
ARM assembly parsing support for RSC instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135713
2011-07-21 22:56:30 +00:00
Jim Grosbach
17806e6636
ARM assembly parsing support for RSB instruction.
...
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
llvm-svn: 135712
2011-07-21 22:37:43 +00:00
Jim Grosbach
2a22c06267
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
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llvm-svn: 135710
2011-07-21 22:29:23 +00:00
Jim Grosbach
b31e60b7c6
ARM parsing and encodings tests for saturating arithmetic insns.
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llvm-svn: 135709
2011-07-21 22:18:28 +00:00
Jim Grosbach
0a8d89242f
ARM assembly parsing POP/PUSH mnemonics.
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Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
llvm-svn: 135702
2011-07-21 19:57:11 +00:00
Jim Grosbach
b2aa2c4a24
Add tests for ARM PKH assembly parsing.
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llvm-svn: 135696
2011-07-21 19:02:03 +00:00
Jim Grosbach
2ea9f25f5f
Add parsing/encoding tests for ARM ORR instruction.
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llvm-svn: 135602
2011-07-20 18:48:53 +00:00
Jim Grosbach
a3fcb962eb
Consolidate ARM NOP encoding test.
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llvm-svn: 135600
2011-07-20 18:39:38 +00:00
Jim Grosbach
614e90a126
ARM parsing and encoding tests for MVN
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llvm-svn: 135599
2011-07-20 18:37:08 +00:00
Jim Grosbach
8d11490771
ARM assembly parsing of MUL instruction.
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Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
llvm-svn: 135596
2011-07-20 18:20:31 +00:00
Jim Grosbach
d25c2cdad7
Tweak ARM assembly parsing and printing of MSR instruction.
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The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Jim Grosbach
97094d8f06
ARM assembly parsing of MRS instruction.
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Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Jim Grosbach
b17d9b12a6
Move mr[r]c[2] ARM tests and tidy up a bit.
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llvm-svn: 135517
2011-07-19 20:28:56 +00:00
Jim Grosbach
69721dce67
ARM testcases for MOVT.
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llvm-svn: 135516
2011-07-19 20:23:25 +00:00
Jim Grosbach
5cc3b4cd9a
ARM assembly parsing for MOV (register).
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Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
llvm-svn: 135513
2011-07-19 20:10:31 +00:00
Jim Grosbach
7c09e3c3f3
ARM assembly parsing for MOV (immediate).
...
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
llvm-svn: 135500
2011-07-19 19:13:28 +00:00
Jim Grosbach
51849920f1
Add some testcases for ARM MLA/MLS instructions.
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llvm-svn: 135196
2011-07-14 21:43:05 +00:00
Jim Grosbach
26e7449443
ARM MCRR/MCRR2 immediate operand range checking.
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llvm-svn: 135192
2011-07-14 21:26:42 +00:00
Jim Grosbach
d37d2025e9
ARM MCR/MCR2 assembly parsing operand constraints.
...
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
llvm-svn: 135189
2011-07-14 21:19:17 +00:00
Jim Grosbach
2f9aeeef3b
Update ARM Assembly of LDM/STM.
...
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
llvm-svn: 135168
2011-07-14 18:35:38 +00:00