47926aff96
Set weight of zero length intervals to infinite to prevent them from being
...
spilled.
llvm-svn: 28220
2006-05-11 07:29:24 +00:00
db6aa4896b
Backing out previous check-in.
...
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
68afff2dcd
Fix some problems linking stuff in libTarget.
...
llvm-svn: 28218
2006-05-11 03:10:15 +00:00
6ad040a6bc
If the live interval legnth is essentially zero, i.e. in every live range
...
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.
llvm-svn: 28217
2006-05-10 22:30:41 +00:00
47a57ac4f9
Update test case
...
llvm-svn: 28216
2006-05-10 19:53:05 +00:00
a36ee4ea34
Two changes:
...
1. Implement InstCombine/deadcode.ll by not adding instructions in unreachable
blocks (due to constants in conditional branches/switches) to the worklist.
This causes them to be deleted before instcombine starts up, leading to
better optimization.
2. In the prepass over instructions, do trivial constprop/dce as we go. This
has the effect of improving the effectiveness of #1 . In addition, it
*significantly* speeds up instcombine on test cases with large amounts of
constant folding code (for example, that produced by code specialization
or partial evaluation). In one example, it speeds up instcombine from
0.0589s to 0.0224s with a release build (a 2.6x speedup).
llvm-svn: 28215
2006-05-10 19:00:36 +00:00
1a0e0c1c9e
New testcase, check that dead code doesn't pessimize instcombine
...
llvm-svn: 28214
2006-05-10 18:56:04 +00:00
b25cb79604
Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which is
...
really a bad codegen bug that LLC happens to get lucky with. I must chat with
Nate for the proper fix.
llvm-svn: 28213
2006-05-10 06:38:32 +00:00
9665ba053f
Templatify RegReductionPriorityQueue
...
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
728c377e0f
Add alloca/malloc ctors that don't take array sizes.
...
llvm-svn: 28211
2006-05-10 04:38:35 +00:00
bb7ff6690f
Add an assertion for a common error
...
llvm-svn: 28210
2006-05-10 04:32:43 +00:00
32982836b6
Watch out for the following case:
...
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.
llvm-svn: 28209
2006-05-10 02:47:57 +00:00
d2b8067748
Fix a load folding bug. It is exposed by a multi- resulting instructions
...
def : Pat<> pattern.
llvm-svn: 28208
2006-05-10 00:05:46 +00:00
1a225d23ae
Fix PR773
...
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
5d779af587
This method doesn't need to be virtual, thanks to Reid for pointing this out.
...
llvm-svn: 28206
2006-05-09 17:29:17 +00:00
f801792e08
Fix a regression in my patch from last night that broke the llvmgcc4 build on
...
ppc
llvm-svn: 28205
2006-05-09 16:41:59 +00:00
2814134a5d
Indent .data/.text in the .s file
...
llvm-svn: 28204
2006-05-09 16:15:00 +00:00
43ddc376fb
Another instruction scheduling test case
...
llvm-svn: 28203
2006-05-09 07:20:24 +00:00
7d693898ee
Add pseudo dependency to force a def&use operand to be scheduled last (unless
...
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".
llvm-svn: 28201
2006-05-09 07:13:34 +00:00
2c74848af1
Debugging info
...
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
fc532fe1b7
Remove a completed entry.
...
llvm-svn: 28199
2006-05-09 06:54:05 +00:00
c39ab4575e
Test case for PR770
...
llvm-svn: 28198
2006-05-09 06:48:12 +00:00
ae45020720
PR 770 - permit coallescing of registers in subset register classes.
...
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
f2925b3b2c
Added sub- register classes information.
...
llvm-svn: 28196
2006-05-09 06:35:30 +00:00
5e7ba0b049
Add sub-register class information.
...
llvm-svn: 28195
2006-05-09 06:34:26 +00:00
4ebc6a2311
Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
...
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
af35b1476e
Implement MASM sections correctly, without a "has masm sections flag" and a
...
bunch of special case code.
llvm-svn: 28193
2006-05-09 05:33:28 +00:00
8c2bfc0659
Oh yeah, there are two of these now, unify both.
...
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
6341df8069
Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
...
of code to be unified.
llvm-svn: 28191
2006-05-09 05:23:12 +00:00
0b7acaf027
MASM doesn't have one of these.
...
llvm-svn: 28190
2006-05-09 05:21:47 +00:00
d36cc2b610
Don't prefix section directives with a tab. Doing so causes blank lines to
...
be emitted to the .s file.
llvm-svn: 28189
2006-05-09 05:19:59 +00:00
e64f764d25
Make the masm codepath work like the normal code path.
...
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
e0006c6794
Preserve prior behavior
...
llvm-svn: 28187
2006-05-09 05:15:24 +00:00
c0f0dfa56f
The MASM asmprinter has been fixed, these hacks are no longer needed.
...
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
d0201946ad
Fix the MASM asmprinter's lies. It does not want to emit code to .text/.data
...
it wants it emitted to _text/_data.
llvm-svn: 28185
2006-05-09 05:12:53 +00:00
8488ba2e41
Split SwitchSection into SwitchTo{Text|Data}Section methods.
...
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
a6212b0fe6
Split SwitchSection into the SwitchTo{Text|Data}Section functions, to better
...
support assemblers that distinguish the two.
llvm-svn: 28183
2006-05-09 04:59:30 +00:00
8587f8885d
Some notes and thoughts to myself
...
llvm-svn: 28182
2006-05-09 04:58:46 +00:00
4fe87d67c4
Patch to make some xforms preserve each other. Patch contributed by
...
Domagoj Babic!
llvm-svn: 28181
2006-05-09 04:13:41 +00:00
357f3e8231
Use the -dumpversion option to llvm-gcc which gives us just the version #
...
and is unlikely to change in future releases. This also simplifies the
parsing of the full and major llvm-gcc version numbers in the script.
llvm-svn: 28180
2006-05-09 00:31:01 +00:00
6d8dd189f6
Move some methods out of line so that MutexGuard.h isn't needed in a public header.
...
llvm-svn: 28179
2006-05-08 22:00:52 +00:00
12b056007e
Move methods out of line so that MutexGuard.h isn't required in the header.
...
llvm-svn: 28178
2006-05-08 22:00:26 +00:00
aa193d80a9
Another bad case I noticed
...
llvm-svn: 28177
2006-05-08 21:39:45 +00:00
5bcea612f4
add a note
...
llvm-svn: 28176
2006-05-08 21:24:21 +00:00
446e1ef26a
Make the case I just checked in stronger. Now we compile this:
...
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
to:
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test2:
add r2, r3, r4
extsh r2, r2
srwi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28175
2006-05-08 21:18:59 +00:00
29062da0ac
Implement and_sext.ll:test3, generating:
...
_test4:
srawi r3, r3, 16
blr
instead of:
_test4:
srwi r2, r3, 16
extsh r3, r2
blr
for:
short test4(unsigned X) {
return (X >> 16);
}
llvm-svn: 28174
2006-05-08 20:59:41 +00:00
536c83f25d
new testcase
...
llvm-svn: 28173
2006-05-08 20:58:58 +00:00
ce6646c366
Yet more readme updating
...
llvm-svn: 28172
2006-05-08 20:54:02 +00:00
2935d8190c
Compile this:
...
short test4(unsigned X) {
return (X >> 16);
}
to:
_test4:
movl 4(%esp), %eax
sarl $16, %eax
ret
instead of:
_test4:
movl $-65536, %eax
andl 4(%esp), %eax
sarl $16, %eax
ret
llvm-svn: 28171
2006-05-08 20:51:54 +00:00
68a45419cc
New note about something bad happening in target independent optimizers
...
llvm-svn: 28170
2006-05-08 20:08:28 +00:00
0eb8f2e496
Proving once again that I am not as smart as the compiler
...
llvm-svn: 28169
2006-05-08 19:09:24 +00:00
9b6d4c2968
Fold more shifts into inserts, and update the README
...
llvm-svn: 28168
2006-05-08 17:38:32 +00:00
78da6792e7
Fold shifts with undef operands.
...
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
10c653744e
When tracking demanded bits, if any bits from the sext of an SRA are demanded,
...
then so is the input sign bit. This fixes mediabench/g721 on X86.
llvm-svn: 28166
2006-05-08 17:22:53 +00:00
d7a19102d1
Make emission of jump tables a bit less conservative; they are now required
...
to be only 31.25% dense, rather than 75% dense.
llvm-svn: 28165
2006-05-08 16:51:36 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
ea10657c08
Move the definition of value_use_iterator::getOperandNo to User.h where the
...
definition of the User class is available, this fixes the build with some
compiler versions.
llvm-svn: 28163
2006-05-08 05:59:36 +00:00
dc996b3f6c
Update some stuff now that the new rlwimi code has gone in
...
llvm-svn: 28162
2006-05-08 02:52:38 +00:00
e5ce5bb6da
Fix PR772
...
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
a35ee93a59
Remove unncessary include
...
llvm-svn: 28160
2006-05-08 01:33:11 +00:00
21c85bc790
This test passes now, remove xfail marker
...
Change test to be a positive test instead of a negative test
llvm-svn: 28159
2006-05-07 18:16:31 +00:00
6732dcd5b3
Typo's
...
llvm-svn: 28158
2006-05-07 10:10:20 +00:00
04196acdcb
Unlike Unix, Windows won't let a file be implicitly replaced via renaming without explicit permission.
...
llvm-svn: 28157
2006-05-07 02:51:51 +00:00
1333cead5b
New rlwimi implementation, which is superior to the old one. There are
...
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
llvm-svn: 28156
2006-05-07 00:23:38 +00:00
cd4a643728
Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us
...
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.
llvm-svn: 28155
2006-05-06 23:48:13 +00:00
4f3de3e33c
Add some more sign propagation cases
...
llvm-svn: 28154
2006-05-06 23:40:29 +00:00
9978476c14
Apply bug fix supplied by Greg Pettyjohn for a bug he found: '<invalid>' is not a legal path on Windows.
...
llvm-svn: 28153
2006-05-06 23:25:53 +00:00
7e7bcf3a54
Simplify some code, add a couple minor missed folds
...
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
751817c54f
constant fold sign_extend_inreg
...
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
2a4d7b845b
remove cases handled elsewhere
...
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
f86075731d
Add some more simple sign bit propagation cases.
...
llvm-svn: 28149
2006-05-06 22:39:59 +00:00
ce9b9fe6eb
Fix some loose ends in MASM support.
...
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
0b8c57ec2b
new testcase we handle right now.
...
llvm-svn: 28147
2006-05-06 18:15:50 +00:00
1ecb2a2dac
Use the new TargetLowering::ComputeNumSignBits method to eliminate
...
sign_extend_inreg operations. Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:
short test(short X, short x) {
int Y = X+x;
return (Y >> 1);
}
short test2(short X, short x) {
int Y = (short)(X+x);
return Y >> 1;
}
into:
_test:
add r2, r3, r4
srawi r3, r2, 1
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r3, r2, 1
blr
instead of:
_test:
add r2, r3, r4
srawi r2, r2, 1
extsh r3, r2
blr
_test2:
add r2, r3, r4
extsh r2, r2
srawi r2, r2, 1
extsh r3, r2
blr
llvm-svn: 28146
2006-05-06 09:30:03 +00:00
7206d74f0c
Add some really really simple code for computing sign-bit propagation.
...
This will certainly be enhanced in the future.
llvm-svn: 28145
2006-05-06 09:27:13 +00:00
1474f16166
Add some new methods for computing sign bit information.
...
llvm-svn: 28144
2006-05-06 09:26:22 +00:00
21cd99024a
When inserting casts, be careful of where we put them. We cannot insert
...
a cast immediately before a PHI node.
This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll
llvm-svn: 28143
2006-05-06 09:10:37 +00:00
cbeb178e14
new testcase
...
llvm-svn: 28142
2006-05-06 09:09:47 +00:00
1d441adfbf
Move some code around.
...
Make the "fold (and (cast A), (cast B)) -> (cast (and A, B))" transformation
only apply when both casts really will cause code to be generated. If one or
both doesn't, then this xform doesn't remove a cast.
This fixes Transforms/InstCombine/2006-05-06-Infloop.ll
llvm-svn: 28141
2006-05-06 09:00:16 +00:00
44f121abc1
new testcase from ghostscript that inf looped instcombine
...
llvm-svn: 28140
2006-05-06 08:58:06 +00:00
6d4a2dc4ad
Teach the X86 backend about non-i32 inline asm register classes.
...
llvm-svn: 28139
2006-05-06 00:29:37 +00:00
86a1467fc0
Fold (trunc (srl x, c)) -> (srl (trunc x), c)
...
llvm-svn: 28138
2006-05-06 00:11:52 +00:00
907e392dba
Fold trunc(any_ext). This gives stuff like:
...
27,28c27
< movzwl %di, %edi
< movl %edi, %ebx
---
> movw %di, %bx
llvm-svn: 28137
2006-05-05 22:56:26 +00:00
57f8c5a387
Shrink shifts when possible.
...
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
0f64932a5c
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE
...
llvm-svn: 28135
2006-05-05 22:32:12 +00:00
8b9e11c110
Print a grouping around inline asm blocks so that we can tell when we are
...
using them.
llvm-svn: 28134
2006-05-05 21:50:04 +00:00
c22d4bede5
Print *some* grouping around inline asm blocks so we know where they are.
...
llvm-svn: 28133
2006-05-05 21:48:50 +00:00
a633c31319
Indent multiline asm strings more nicely
...
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
44a73e9fa5
Teach the code generator to use cvtss2sd as extload f32 -> f64
...
llvm-svn: 28131
2006-05-05 21:35:18 +00:00
3d26577396
Fold (fpext (load x)) -> (extload x)
...
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
3e3f2c63c3
More aggressively sink GEP offsets into loops. For example, before we
...
generated:
movl 8(%esp), %eax
movl %eax, %edx
addl $4316, %edx
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, (%edx)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
movl %edx, 4460(%eax)
ret
...
Now we generate:
movl 8(%esp), %eax
cmpb $1, %cl
ja LBB1_2 #cond_false
LBB1_1: #cond_true
movl L_QuantizationTables720$non_lazy_ptr, %ecx
movl %ecx, 4316(%eax)
movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
movl %ecx, 4460(%eax)
ret
... which uses one fewer register.
llvm-svn: 28129
2006-05-05 21:17:49 +00:00
e745c7de0e
Fix an infinite loop compiling oggenc last night.
...
llvm-svn: 28128
2006-05-05 20:51:30 +00:00
52c22512b9
Need extload patterns after Chris' DAG combiner changes
...
llvm-svn: 28127
2006-05-05 08:23:07 +00:00
3af1053488
Implement InstCombine/cast.ll:test29
...
llvm-svn: 28126
2006-05-05 06:39:07 +00:00
c9043ef728
New testcase
...
llvm-svn: 28125
2006-05-05 06:38:40 +00:00
25a5283a86
Fold some common code.
...
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
002ee91457
Implement:
...
// fold (and (sext x), (sext y)) -> (sext (and x, y))
// fold (or (sext x), (sext y)) -> (sext (or x, y))
// fold (xor (sext x), (sext y)) -> (sext (xor x, y))
// fold (and (aext x), (aext y)) -> (aext (and x, y))
// fold (or (aext x), (aext y)) -> (aext (or x, y))
// fold (xor (aext x), (aext y)) -> (aext (xor x, y))
llvm-svn: 28123
2006-05-05 06:31:05 +00:00
5ac4293606
Pull and through and/or/xor. This compiles some bitfield code to:
...
mov EAX, DWORD PTR [ESP + 4]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
or EDX, ECX
and EDX, -2147483648
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
ret
instead of:
sub ESP, 4
mov DWORD PTR [ESP], ESI
mov EAX, DWORD PTR [ESP + 8]
mov ECX, DWORD PTR [EAX]
mov EDX, ECX
add EDX, EDX
mov ESI, ECX
and ESI, -2147483648
and EDX, -2147483648
or EDX, ESI
and ECX, 2147483647
or EDX, ECX
mov DWORD PTR [EAX], EDX
mov ESI, DWORD PTR [ESP]
add ESP, 4
ret
llvm-svn: 28122
2006-05-05 06:10:43 +00:00
812646aa0c
Implement a variety of simplifications for ANY_EXTEND.
...
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
8d6fc20181
Factor some code, add these transformations:
...
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
// fold (or (trunc x), (trunc y)) -> (trunc (or x, y))
// fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))
llvm-svn: 28120
2006-05-05 05:51:50 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
304bbf3b1d
New note, Nate, please check to see if I'm full of it :)
...
llvm-svn: 28118
2006-05-05 05:36:15 +00:00
78a7f0e05e
Fix VC++ compilation error.
...
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
dec86e74ff
Somehow, I missed this part of the checkin a couple days ago
...
llvm-svn: 28116
2006-05-05 01:13:11 +00:00
7a3ecf7993
Sink noop copies into the basic block that uses them. This reduces the number
...
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.
This reduces the load on the coallescer and register allocator. For example
on a codec on X86, we went from:
1643 asm-printer - Number of machine instrs printed
419 liveintervals - Number of loads/stores folded into instructions
1144 liveintervals - Number of identity moves eliminated after coalescing
1022 liveintervals - Number of interval joins performed
282 liveintervals - Number of intervals after coalescing
1304 liveintervals - Number of original intervals
86 regalloc - Number of times we had to backtrack
1.90232 regalloc - Ratio of intervals processed over total intervals
40 spiller - Number of values reused
182 spiller - Number of loads added
121 spiller - Number of stores added
132 spiller - Number of register spills
6 twoaddressinstruction - Number of instructions commuted to coalesce
360 twoaddressinstruction - Number of two-address instructions
to:
1636 asm-printer - Number of machine instrs printed
403 liveintervals - Number of loads/stores folded into instructions
1155 liveintervals - Number of identity moves eliminated after coalescing
1033 liveintervals - Number of interval joins performed
279 liveintervals - Number of intervals after coalescing
1312 liveintervals - Number of original intervals
76 regalloc - Number of times we had to backtrack
1.88998 regalloc - Ratio of intervals processed over total intervals
1 spiller - Number of copies elided
41 spiller - Number of values reused
191 spiller - Number of loads added
114 spiller - Number of stores added
128 spiller - Number of register spills
4 twoaddressinstruction - Number of instructions commuted to coalesce
356 twoaddressinstruction - Number of two-address instructions
On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted. It increases the number
of register coallesces.
llvm-svn: 28115
2006-05-05 01:04:50 +00:00
a0c3ec513d
Add a helper method.
...
llvm-svn: 28114
2006-05-05 00:51:42 +00:00
34d26c38b2
wrap long line
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llvm-svn: 28113
2006-05-04 23:35:31 +00:00
b6277c510c
Adjust to use proper TargetData copy ctor
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llvm-svn: 28112
2006-05-04 21:18:40 +00:00
660d80effe
Fix this to be a proper copy ctor
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llvm-svn: 28111
2006-05-04 21:17:35 +00:00
abdf4d569c
Final pass of minor cleanups for MachineInstr
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llvm-svn: 28110
2006-05-04 19:36:09 +00:00
9add880566
Initial support for register pressure aware scheduling. The register reduction
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scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.
llvm-svn: 28108
2006-05-04 19:16:39 +00:00
53af9da363
Remove redundancy and a level of indirection when creating machine operands
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llvm-svn: 28107
2006-05-04 19:14:44 +00:00
6b18d20c73
Move register numbers out of "extra" into "contents". Other minor cleanup.
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llvm-svn: 28106
2006-05-04 18:25:20 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
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llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
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llvm-svn: 28104
2006-05-04 18:05:43 +00:00
700cd27e83
remove hasAllocatedReg
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llvm-svn: 28103
2006-05-04 17:56:20 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fb29692055
Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll
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llvm-svn: 28101
2006-05-04 17:33:35 +00:00
618ff2dc4e
new testcase that crashes the instcombine pass
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llvm-svn: 28100
2006-05-04 17:33:24 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
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llvm-svn: 28099
2006-05-04 17:21:20 +00:00
15c52bda1d
Change "value" in MachineOperand to be a GlobalValue, as that is the only
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thing that can be in it. Remove a dead method.
llvm-svn: 28098
2006-05-04 17:02:51 +00:00
13d5f3eb05
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
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Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
llvm-svn: 28097
2006-05-04 16:56:45 +00:00
06041abeb6
Make external globals public; other minor cleanup.
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llvm-svn: 28096
2006-05-04 16:20:22 +00:00
f812a4fa75
Make Intel syntax the default when LLVM is built with VC++.
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llvm-svn: 28095
2006-05-04 16:19:27 +00:00
ee64b6b40f
Remove a bunch more dead V9 specific stuff
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llvm-svn: 28094
2006-05-04 01:26:39 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
6e663f1c1e
Remove some more V9-specific stuff.
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llvm-svn: 28092
2006-05-04 00:49:59 +00:00
9f6639b64d
Remove some more unused stuff from MachineInstr that was leftover from V9.
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llvm-svn: 28091
2006-05-04 00:44:25 +00:00
2aef59f123
Simplify handling of relocations
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llvm-svn: 28090
2006-05-04 00:42:08 +00:00
8b1cde2bbe
Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when
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movlps cannot be used (e.g. when load from m64 has multiple uses).
llvm-svn: 28089
2006-05-03 20:32:03 +00:00
e3a9c70ba0
Change from using MachineRelocation ctors to using static methods
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in MachineRelocation to create Relocations.
llvm-svn: 28088
2006-05-03 20:30:20 +00:00
005d7174c8
minor cleanups, no functionality change
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llvm-svn: 28087
2006-05-03 18:55:56 +00:00
9b9dc59813
Cleanup the internal implementation of MachineRelocation. No interface or
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functionality changes.
llvm-svn: 28086
2006-05-03 18:52:31 +00:00
bf98e9f001
Attempt to get this script working on Darwin.
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llvm-svn: 28085
2006-05-03 18:16:01 +00:00
76a0a8aa37
For PR764:
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Don't check in the LibDeps.txt and FinalLibDeps.txt files to CVS because
the content differs from platform to platform. Instead, adjust the makefile
so that a dummy llvm-config is built if Perl is not available.
llvm-svn: 28084
2006-05-03 17:49:50 +00:00
9e68942d78
inline a simple method
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llvm-svn: 28083
2006-05-03 17:21:32 +00:00
1d8ee1fc80
Suck block address tracking out of targets into the JIT Emitter. This
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simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.
llvm-svn: 28082
2006-05-03 17:10:41 +00:00
9954bc9c19
Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms.
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llvm-svn: 28081
2006-05-03 05:48:41 +00:00
43b1ed7e3d
Teach the x86 jit how to handle jump tables not directly used by a jump
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instruction.
llvm-svn: 28080
2006-05-03 04:52:47 +00:00
df4883971e
Finish up the initial jump table implementation by allowing jump tables to
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not be 100% dense. Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.
llvm-svn: 28079
2006-05-03 03:48:02 +00:00
7bd487fe41
A few instruction scheduling test cases.
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llvm-svn: 28077
2006-05-03 02:11:36 +00:00
ffef8b9412
Bottom up register pressure reduction work: clean up some hacks and enhanced
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the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)
llvm-svn: 28076
2006-05-03 02:10:45 +00:00
386fb9b0fd
Set isStore of instructions with ISD::TRUNCSTORE root node.
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llvm-svn: 28075
2006-05-03 02:08:34 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
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This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
37c39b9c62
Align function bodies correctly.
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llvm-svn: 28073
2006-05-03 01:03:20 +00:00
7150a7038a
Add a new emitAlignment method
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llvm-svn: 28072
2006-05-03 01:01:51 +00:00
77fe5b4459
Simplify some code. Don't add memory blocks to the Blocks list twice.
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llvm-svn: 28071
2006-05-03 00:54:49 +00:00
667a056e11
Add assertions that verify that the actual arguments to a call or invoke match
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the prototype of the called function.
llvm-svn: 28070
2006-05-03 00:48:22 +00:00
d8b192ba3b
Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
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llvm-svn: 28069
2006-05-03 00:32:55 +00:00
0267807ddc
Keep the alpha JIT similar to the PPC/X86 jits
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llvm-svn: 28068
2006-05-03 00:31:21 +00:00
Evan Cheng