maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
273,582 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

9 Commits

Author SHA1 Message Date
Simon Pilgrim 2911296f10 [DAGCombiner] Match ISD::SRL non-uniform constant vectors patterns using predicates. 
Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds

llvm-svn: 308602
 2017-07-20 11:03:30 +00:00
Simon Pilgrim 77ce072f6b [X86][AVX] Regenerate combine tests with constant broadcast comments 
llvm-svn: 308128
 2017-07-16 11:36:11 +00:00
Simon Pilgrim c29af824bf [DAGCombiner] Add vector support to fold (shl/srl 0, x) -> 0 
llvm-svn: 302641
 2017-05-10 12:34:27 +00:00
Simon Pilgrim 7d65b66962 [DAGCombiner] Add vector support for (srl (trunc (srl x, c1)), c2) combine. 
llvm-svn: 301305
 2017-04-25 12:40:45 +00:00
Sanjay Patel a0d8a278a7 [x86] use a single shufps when it can save instructions 
This is a tiny patch with a big pile of test changes.
This partially fixes PR27885:
https://llvm.org/bugs/show_bug.cgi?id=27885

My motivating case looks like this:

  - vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
  - vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
  - vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]

  + vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]

And this happens several times in the diffs. For chips with domain-crossing penalties,
the instruction count and size reduction should usually overcome any potential 
domain-crossing penalty due to using an FP op in a sequence of int ops. For chips such
as recent Intel big cores and Atom, there is no domain-crossing penalty for shufps, so
using shufps is a pure win.

So the test case diffs all appear to be improvements except one test in 
vector-shuffle-combining.ll where we miss an opportunity to use a shift to generate 
zero elements and one test in combine-sra.ll where multiple uses prevent the expected
shuffle combining.

Differential Revision: https://reviews.llvm.org/D27692

llvm-svn: 289837
 2016-12-15 18:03:38 +00:00
Sanjay Patel 9ca028c2d6 [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant 
llvm-svn: 284953
 2016-10-23 23:13:31 +00:00
Simon Pilgrim 618d3aedaf [DAGCombiner] Add general constant vector support to (srl (shl x, c), c) -> (and x, cst2) 
We already supported scalar constant / splatted constant vector - now accepts any (non opaque) constant scalar / vector

llvm-svn: 284717
 2016-10-20 11:10:21 +00:00
Simon Pilgrim b2ca2505cc [DAGCombine] Generalize distributeTruncateThroughAnd to work with any non-opaque constant or constant vector 
llvm-svn: 284574
 2016-10-19 08:57:37 +00:00
Simon Pilgrim 476560aac4 [X86][SSE] Added vector lshr/shl combine tests 
This doesn't cover all combines in DAGCombiner::visitSRL/visitSHL yet, but identifies several cases where we fail to combine vectors (or non-splatted) vectors

llvm-svn: 284518
 2016-10-18 19:28:12 +00:00