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25 Commits

Author SHA1 Message Date
Craig Topper da9fe56bf6 [X86] Add command line switches for xsave/xsaveopt/xsavec/xsaves. Macro defines for the same. And add the flags to correct CPU names. 
llvm-svn: 250368
 2015-10-15 05:23:38 +00:00
Eric Christopher f43966f38d Make the msse4/mno-sse4 flags aliases of the maximum sse values 
they enable/disable.

This fixes two things:

a) sse4 isn't actually a target feature, don't treat it as one.
b) we weren't correctly disabling sse4.1 when we'd pass -mno-sse4
   after enabling it, thus passing preprocessor directives and
   (soon) passing the function attribute as well when we shouldn't.

llvm-svn: 233223
 2015-03-25 22:09:26 +00:00
Robert Khasanov 50e6f58b4f [x86] Enable broadwell target in clang. 
Added -madx option

llvm-svn: 218116
 2014-09-19 09:53:48 +00:00
Robert Khasanov 3b6616c3a3 [SKX] Enabling SKX target (Skylake server chip) 
a) add SKX support to Clang driver;
b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests

Patch by Zinovy Nis <zinovy.y.nis@intel.com>

llvm-svn: 214306
 2014-07-30 13:53:40 +00:00
Nico Rieck 140db2767b Fix broken RUN lines 
llvm-svn: 201475
 2014-02-16 07:28:32 +00:00
Yunzhong Gao 6108936fa6 Enabling 3DNow! prefetch instruction support for a few AMD processors in the 
clang front end. This change will allow the __PRFCHW__ macro to be set on these
processors and hence include prfchwintrin.h in x86intrin.h header. Support for
the intrinsic itself seems to have already been added in r178041.

Differential Revision: http://llvm-reviews.chandlerc.com/D1934

llvm-svn: 192829
 2013-10-16 19:07:02 +00:00
Nick Lewycky 50e8f480ea Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when 
it is enabled. Also enable it on the same architectures that GCC does.

llvm-svn: 192045
 2013-10-05 20:14:27 +00:00
Yunzhong Gao 1f6aeebe76 Adding -mtbm and -mno-tbm command line options to the clang front end for the 
x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is
enabled. Otherwise there should be no functionality change to existing features.

Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693

llvm-svn: 191326
 2013-09-24 19:00:58 +00:00
Ben Langmuir 58078d0103 Add C intrinsics for Intel SHA Extensions 
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.

llvm-svn: 190999
 2013-09-19 13:22:04 +00:00
Craig Topper 5f79e2661d Disabling sse2 should disable aes and pclmul support. 
llvm-svn: 190977
 2013-09-19 00:01:05 +00:00
Craig Topper 31db3a2efc Make F16C feature imply AVX. Matches GCC behavior. 
llvm-svn: 190776
 2013-09-16 04:54:13 +00:00
Craig Topper c0070a4320 Fix a bug where -msse followed by -mno-sse would leave MMX enabled. 
llvm-svn: 190496
 2013-09-11 06:48:53 +00:00
Craig Topper 7481d8aa17 Separate popcnt and sse4.2 feature control somewhat to match gcc behavior. 
Enabling sse4.2 will implicitly enable popcnt unless popcnt is explicitly disabled.
Disabling sse4.2 will not disable popcnt if popcnt is explicitly enabled.

llvm-svn: 190387
 2013-09-10 06:55:47 +00:00
Craig Topper 258a86802a Add test cases for avx512 feature flags. Fix typo in avx512pf options. 
llvm-svn: 188984
 2013-08-22 04:32:55 +00:00
Rafael Espindola 0221d8636e Don't disable SSE4A when disabling AVX. 
Thanks for Craig Topper for noticing it.

llvm-svn: 188902
 2013-08-21 13:28:02 +00:00
Rafael Espindola db0fcfbfae Centralize the logic for handling -m* options and fix pr16943. 
This moves the logic for handling -mfoo -mno-foo from the driver to -cc1. It
also changes -cc1 to apply the options in order, fixing pr16943.

The handling of -mno-mmx -msse is now an explicit special case.

llvm-svn: 188817
 2013-08-20 18:57:55 +00:00
Rafael Espindola 80a99478bd Convert test to FileCheck. 
llvm-svn: 185645
 2013-07-04 15:08:20 +00:00
Sebastian Pop 422377cfd3 rename -ccc-host-triple into -target 
llvm-svn: 148582
 2012-01-20 22:01:23 +00:00
Eli Friedman d749c6bf2e Revert r148138; it's causing test failures. 
llvm-svn: 148141
 2012-01-13 21:33:06 +00:00
Sebastian Pop 9a8d528ddf rename -ccc-host-triple into -target 
llvm-svn: 148138
 2012-01-13 20:37:02 +00:00
Daniel Dunbar 5618e98f33 Update tests to use %clang instead of 'clang', and forcibly disable use of ' 
clang ' or ' clang -cc1 ' or ' clang-cc ' in test lines (by substituting them to
garbage).

llvm-svn: 91460
 2009-12-15 22:01:24 +00:00
Daniel Dunbar 34546ce43d Remove RUN: true lines. 
llvm-svn: 86432
 2009-11-08 01:47:25 +00:00
Daniel Dunbar 8b57697954 Eliminate &&s in tests. 
- 'for i in $(find . -type f); do sed -e 's#\(RUN:.*[^ ]\) *&& *$#\1#g' $i | FileUpdate $i; done', for the curious.

llvm-svn: 86430
 2009-11-08 01:45:36 +00:00
Daniel Dunbar f9d90275f9 Handle -march for the LLVM recognized cpu names. 
- x86 target feature handling should not be feature complete, even if
   the code quality is lacking.

llvm-svn: 71123
 2009-05-06 21:56:32 +00:00
Daniel Dunbar bb36aed06b More x86 target feature support. 
- Apologies for the extremely gross code duplication, I want to get
   this working and then decide how to get this information out of the
   back end.

 - This replaces -m[no-]sse4[12] by -m[no-]sse4, it appears gcc
   doesn't distinguish them?

 - -msse, etc. now properly disable/enable related features.

 - Don't always define __SSE3__...

 - The main missing functionality bit here is that we don't initialize
   the features based on the CPU for all -march options.

llvm-svn: 71117
 2009-05-06 21:07:50 +00:00