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7 Commits

Author SHA1 Message Date
Andrew Trick 8523b16ff5 Instruction scheduling itinerary for Intel Atom. 
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.

Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.

Adds a test to verify that the scheduler is working.

Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.

Patch by Preston Gurd!

llvm-svn: 149558
 2012-02-01 23:20:51 +00:00
Jakob Stoklund Olesen 17d4f9bbcc Prepare remaining tests for -join-physreg going away. 
llvm-svn: 130893
 2011-05-04 23:54:59 +00:00
Jakob Stoklund Olesen bd09d45489 Fix register-dependent X86 tests. 
llvm-svn: 128867
 2011-04-05 00:32:44 +00:00
NAKAMURA Takumi a1e2ed5f1b Relax expressions and add explicit triplets -linux and -win32. 
llvm-svn: 126210
 2011-02-22 07:21:08 +00:00
Dan Gohman f1cf963c64 Loosen up this test so that it doesn't depend as much on register 
allocation details.

llvm-svn: 106599
 2010-06-22 23:32:47 +00:00
Dan Gohman 1081f1a0f5 Fix OptimizeMax to handle an odd case where one of the max operands 
is another max which folds. This fixes PR7454.

llvm-svn: 106594
 2010-06-22 23:07:13 +00:00
Dan Gohman 534ba376f6 Generalize LSR's OptimizeMax to handle the new kinds of max expressions 
that indvars may use, now that indvars is recognizing le and ge loops.

llvm-svn: 102235
 2010-04-24 03:13:44 +00:00