Commit Graph

155974 Commits

Author SHA1 Message Date
Rafael Espindola d9401d664b Remove dead code.
llvm-svn: 188802
2013-08-20 14:18:24 +00:00
Ed Maste a6b4c77123 Include checksum in non-ack mode
Patch from Abid, Hafiz.

llvm-svn: 188801
2013-08-20 14:12:58 +00:00
NAKAMURA Takumi 166b874696 UniqueHeaderNameTest.cpp: Appease valgrind.
llvm::sys::path::native(dst, dst) might be overridden-safe in most cases, though.

llvm-svn: 188800
2013-08-20 14:02:38 +00:00
Rafael Espindola e62e279f97 Refactor the x86 feature handling.
This removes the very long chains of
Feature["avx"] = Feature["sse42"] = ... = true;

llvm-svn: 188799
2013-08-20 13:44:29 +00:00
Vladimir Medic 9bad0d33b6 Fix style issues in AsmParser.cpp
llvm-svn: 188798
2013-08-20 13:33:18 +00:00
Tim Northover 244950d641 ARM: add test for last commit
This time I managed to forget the test.

Patch still by Stephen Kelly.

llvm-svn: 188797
2013-08-20 13:19:43 +00:00
Tim Northover b9facf72aa ARM: default to arm1176jzf-s for hard-float platforms.
It makes no sense to try and compile for arm7tdmi when we're targeting
something like gnueabihf. Although not strictly the most basic hardware
conceivable, I believe arm1176jzf-s is a reasonable compromise (that can always
be overridden explicitly if needed) since it's still in reasonably common use
unlike earlier cores.

Patch by Stephen Kelly.

llvm-svn: 188796
2013-08-20 13:13:38 +00:00
Guillaume Papin 1593c7b20a Revert "cpp11-migrate: Add a class to support include directives modifications"
This reverts commit r188791.

The Windows bots are still broken.

llvm-svn: 188795
2013-08-20 13:05:57 +00:00
Daniel Jasper 2b41a82e61 clang-format: Format enum struct/class like enum.
Patch by Joe Hermaszewski. Thank you!

llvm-svn: 188794
2013-08-20 12:42:50 +00:00
Daniel Jasper b55acad91c clang-format: Additional options for spaces around parentheses.
This patch adds four new options to control:
- Spaces after control keyworks (if(..) vs if (..))
- Spaces in empty parentheses (f( ) vs f())
- Spaces in c-style casts (( int )1.0 vs (int)1.0)
- Spaces in other parentheses (f(a) vs f( a ))

Patch by Joe Hermaszewski. Thank you for working on this!

llvm-svn: 188793
2013-08-20 12:36:34 +00:00
Benjamin Kramer 5e5e5a92b4 ARCMigrate depends on the static analyzer.
llvm-svn: 188792
2013-08-20 12:33:59 +00:00
Guillaume Papin f240481b99 cpp11-migrate: Add a class to support include directives modifications
The IncludeDirectives class helps with detecting and modifying #include
directives. For now it allows the users to add angled-includes in a source file.
This is a start for this class that will evolve in the future to add more
functionality.

This should fix the reverted commit r188610 (buildbot failures on Windows).

llvm-svn: 188791
2013-08-20 12:30:26 +00:00
NAKAMURA Takumi 99941a9558 clang/test/Driver/cl-options.c: Remove the feature "clang-driver". It has been working since r188331.
llvm-svn: 188790
2013-08-20 12:16:48 +00:00
NAKAMURA Takumi 5a13d0f175 clang/test/Driver: Remove the feature "clang-driver" since gcc-as has not been used with -integrated-as since r177360.
llvm-svn: 188789
2013-08-20 12:16:42 +00:00
NAKAMURA Takumi 422a3b4570 clang/test/Driver: Remove the feature "clang-driver" in three tests since they might work as expected since their first commit.
llvm-svn: 188788
2013-08-20 12:16:35 +00:00
Elena Demikhovsky 540d582594 AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQ
llvm-svn: 188786
2013-08-20 11:00:29 +00:00
Daniel Sanders b545c253d6 [mips][msa] Added fexdo, fexup[lr] builtins
llvm-svn: 188784
2013-08-20 09:47:12 +00:00
Daniel Sanders 4260527f5f [mips][msa] Removed fcge, fcgt, fsge, fsgt
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
2013-08-20 09:41:47 +00:00
Richard Sandiford 2bf7b8cc4e [SystemZ] Update README
We now use MVST, CLST and SRST for the obvious cases.

llvm-svn: 188781
2013-08-20 09:40:35 +00:00
Richard Sandiford 6f6d55161b [SystemZ] Use SRST to optimize memchr
SystemZTargetLowering::emitStringWrapper() previously loaded the character
into R0 before the loop and made R0 live on entry.  I'd forgotten that
allocatable registers weren't allowed to be live across blocks at this stage,
and it confused LiveVariables enough to cause a miscompilation of f3 in
memchr-02.ll.

This patch instead loads R0 in the loop and leaves LICM to hoist it
after RA.  This is actually what I'd tried originally, but I went for
the manual optimisation after noticing that R0 often wasn't being hoisted.
This bug forced me to go back and look at why, now fixed as r188774.

We should also try to optimize null checks so that they test the CC result
of the SRST directly.  The select between null and the SRST GPR result could
then usually be deleted as dead.

llvm-svn: 188779
2013-08-20 09:38:48 +00:00
Benjamin Kramer 5a71250113 memcmp is not a valid way to compare structs with padding in them.
llvm-svn: 188778
2013-08-20 09:27:31 +00:00
Daniel Sanders f2a0f1d133 [mips][msa] Added insve
llvm-svn: 188777
2013-08-20 09:22:54 +00:00
Ed Maste 0584d7fc34 Fix crash when connecting to gdbserver without loading a file first.
Patch from Abid, Hafiz.

llvm-svn: 188776
2013-08-20 09:17:13 +00:00
Richard Sandiford bdd81d76f8 Fix test typo and add usual "br %r14" test
llvm-svn: 188775
2013-08-20 09:14:46 +00:00
Richard Sandiford 96aa93d5f1 Fix overly pessimistic shortcut in post-RA MachineLICM
Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers
and TermRegs.  When it sees a definition of R it adds all aliases of R
to the corresponding set, so that when it needs to test for membership
it only needs to test a single register, rather than worrying about
aliases there too.  E.g. the final candidate loop just has:

    unsigned Def = Candidates[i].Def;
    if (!PhysRegClobbers.test(Def) && ...) {

to test whether register Def is multiply defined.

However, there was also a shortcut in ProcessMI to make sure we didn't
add candidates if we already knew that they would fail the final test.
This shortcut was more pessimistic than the final one because it
checked whether _any alias_ of the defined register was multiply defined.
This is too conservative for targets that define register pairs.
E.g. on z, R0 and R1 are sometimes used as a pair, so there is a
128-bit register that aliases both R0 and R1.  If a loop used
R0 and R1 independently, and the definition of R0 came first,
we would be able to hoist the R0 assignment (because that used
the final test quoted above) but not the R1 assignment (because
that meant we had two definitions of the paired R0/R1 register
and would fail the shortcut in ProcessMI).

This patch just uses the same check for the ProcessMI shortcut as
we use in the final candidate loop.

llvm-svn: 188774
2013-08-20 09:11:13 +00:00
Tim Northover f79c3a5aef ARM: implement some simple f64 materializations.
Previously we used a const-pool load for virtually all 64-bit floating values.
Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov"
instructions of one stripe or another.

llvm-svn: 188773
2013-08-20 08:57:11 +00:00
Michael Gottesman dc985ef0af [stackprotector] Small cleanup.
llvm-svn: 188772
2013-08-20 08:56:28 +00:00
Michael Gottesman 76c44be14a [stackprotector] Small Bit of computation hoisting.
llvm-svn: 188771
2013-08-20 08:56:26 +00:00
Michael Gottesman 1977d15e02 [stackprotector] Added significantly longer comment to FindPotentialTailCall to make clear its relationship to llvm::isInTailCallPosition.
llvm-svn: 188770
2013-08-20 08:56:23 +00:00
Michael Gottesman 62c5d714a1 Removed trailing whitespace.
llvm-svn: 188769
2013-08-20 08:46:16 +00:00
Michael Gottesman 56e246b1a1 [stackprotector] Removed stale TODO.
llvm-svn: 188768
2013-08-20 08:46:13 +00:00
Daniel Sanders 869bdad93a [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v
llvm-svn: 188767
2013-08-20 08:38:21 +00:00
Michael Gottesman 5e57068b7a [stackprotector] Added support for emitting the llvm intrinsic stack protector check.
rdar://13935163

llvm-svn: 188766
2013-08-20 08:36:53 +00:00
Michael Gottesman ce0e4c263b [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall.
This allows me to use returnTypeIsEligibleForTailCall in the stack protector pass.

rdar://13935163

llvm-svn: 188765
2013-08-20 08:36:50 +00:00
Craig Topper af0ca63cec Rename __AVX512__ to __AVX512F__
llvm-svn: 188764
2013-08-20 07:52:37 +00:00
Michael Gottesman 3f3404fd3a [autotools->cmake] Added support for building clang with an order file.
llvm-svn: 188763
2013-08-20 07:41:18 +00:00
Craig Topper 007b059c33 Change 'avx512' to 'avx-512' to match llvm backend.
llvm-svn: 188762
2013-08-20 07:39:54 +00:00
Michael Gottesman f7e1203d95 Remove unused variables that crept in.
llvm-svn: 188761
2013-08-20 07:17:27 +00:00
Michael Gottesman 23a3567bf1 [autotools->cmake] Move add_subdirectory(test) inside CLANG_INCLUDE_TESTS to match the behavior of the LLVM where LLVM_INCLUDE_TESTS controls whether tests is included.
llvm-svn: 188760
2013-08-20 07:09:54 +00:00
Michael Gottesman 794315b65a [autotools->cmake] Added support for creating the clang driver plist for OS X.
llvm-svn: 188759
2013-08-20 07:09:51 +00:00
Craig Topper 449314e1ec Add AVX-512 feature flag and knl cpu to clang.
llvm-svn: 188758
2013-08-20 07:09:39 +00:00
Craig Topper 33b4cde2f2 Revert r188756 because some other changes snuck in with it.
llvm-svn: 188757
2013-08-20 07:07:29 +00:00
Craig Topper ffb7180e96 Add AVX-512 feature flag and knl cpu to clang.
llvm-svn: 188756
2013-08-20 07:05:05 +00:00
Michael Gottesman b27f0f1f6b Teach selectiondag how to handle the stackprotectorcheck intrinsic.
Previously, generation of stack protectors was done exclusively in the
pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated
splitting basic blocks at the IR level to create the success/failure basic
blocks in the tail of the basic block in question. As a result of this,
calls that would have qualified for the sibling call optimization were no
longer eligible for optimization since said calls were no longer right in
the "tail position" (i.e. the immediate predecessor of a ReturnInst
instruction).

Then it was noticed that since the sibling call optimization causes the
callee to reuse the caller's stack, if we could delay the generation of
the stack protector check until later in CodeGen after the sibling call
decision was made, we get both the tail call optimization and the stack
protector check!

A few goals in solving this problem were:

  1. Preserve the architecture independence of stack protector generation.

  2. Preserve the normal IR level stack protector check for platforms like
     OpenBSD for which we support platform specific stack protector
     generation.

The main problem that guided the present solution is that one can not
solve this problem in an architecture independent manner at the IR level
only. This is because:

  1. The decision on whether or not to perform a sibling call on certain
     platforms (for instance i386) requires lower level information
     related to available registers that can not be known at the IR level.

  2. Even if the previous point were not true, the decision on whether to
     perform a tail call is done in LowerCallTo in SelectionDAG which
     occurs after the Stack Protector Pass. As a result, one would need to
     put the relevant callinst into the stack protector check success
     basic block (where the return inst is placed) and then move it back
     later at SelectionDAG/MI time before the stack protector check if the
     tail call optimization failed. The MI level option was nixed
     immediately since it would require platform specific pattern
     matching. The SelectionDAG level option was nixed because
     SelectionDAG only processes one IR level basic block at a time
     implying one could not create a DAG Combine to move the callinst.

To get around this problem a few things were realized:

  1. While one can not handle multiple IR level basic blocks at the
     SelectionDAG Level, one can generate multiple machine basic blocks
     for one IR level basic block. This is how we handle bit tests and
     switches.

  2. At the MI level, tail calls are represented via a special return
     MIInst called "tcreturn". Thus if we know the basic block in which we
     wish to insert the stack protector check, we get the correct behavior
     by always inserting the stack protector check right before the return
     statement. This is a "magical transformation" since no matter where
     the stack protector check intrinsic is, we always insert the stack
     protector check code at the end of the BB.

Given the aforementioned constraints, the following solution was devised:

  1. On platforms that do not support SelectionDAG stack protector check
     generation, allow for the normal IR level stack protector check
     generation to continue.

  2. On platforms that do support SelectionDAG stack protector check
     generation:

    a. Use the IR level stack protector pass to decide if a stack
       protector is required/which BB we insert the stack protector check
       in by reusing the logic already therein. If we wish to generate a
       stack protector check in a basic block, we place a special IR
       intrinsic called llvm.stackprotectorcheck right before the BB's
       returninst or if there is a callinst that could potentially be
       sibling call optimized, before the call inst.

    b. Then when a BB with said intrinsic is processed, we codegen the BB
       normally via SelectBasicBlock. In said process, when we visit the
       stack protector check, we do not actually emit anything into the
       BB. Instead, we just initialize the stack protector descriptor
       class (which involves stashing information/creating the success
       mbbb and the failure mbb if we have not created one for this
       function yet) and export the guard variable that we are going to
       compare.

    c. After we finish selecting the basic block, in FinishBasicBlock if
       the StackProtectorDescriptor attached to the SelectionDAGBuilder is
       initialized, we first find a splice point in the parent basic block
       before the terminator and then splice the terminator of said basic
       block into the success basic block. Then we code-gen a new tail for
       the parent basic block consisting of the two loads, the comparison,
       and finally two branches to the success/failure basic blocks. We
       conclude by code-gening the failure basic block if we have not
       code-gened it already (all stack protector checks we generate in
       the same function, use the same failure basic block).

llvm-svn: 188755
2013-08-20 07:00:16 +00:00
Craig Topper 7a8cf01090 Fix formatting. No functional change.
llvm-svn: 188746
2013-08-20 05:23:59 +00:00
Craig Topper e13a066c94 Add AVX-512 and related features to the CPUID detection code.
llvm-svn: 188745
2013-08-20 05:22:42 +00:00
Craig Topper fd2b389263 Move AVX and non-AVX replication inside a couple multiclasses to avoid repeating each instruction for both individually.
llvm-svn: 188743
2013-08-20 04:24:14 +00:00
Craig Topper 998a39aeed Add an error check for a typo I accidentally made in a td file that caused an assert to fire.
llvm-svn: 188742
2013-08-20 04:22:09 +00:00
Bill Schmidt f381afc906 [PowerPC] More refactoring prior to real PPC emitPrologue/Epilogue changes.
(Patch committed on behalf of Mark Minich, whose log entry follows.)

This is a continuation of the refactorings performed in svn rev 188573
(see that rev's comments for more detail).

This is my stage 2 refactoring: I combined the emitPrologue() &
emitEpilogue() PPC32 & PPC64 code into a single flow, simplifying a
lot of the code since in essence the PPC32 & PPC64 code generation
logic is the same, only the instruction forms are different (in most
cases). This simplification is necessary because my functional changes
(yet to come) add significant complexity, and without the
simplification of my stage 2 refactoring, the overall complexity of
both emitPrologue() & emitEpilogue() would have become almost
intractable for most mortal programmers (like me).

This submission was intended to be a pure refactoring (no functional
changes whatsoever). However, in the process of combining the PPC32 &
PPC64 flows, I spotted a difference that I believe is a bug (see svn
rev 186478 line 863, or svn rev 188573 line 888): This line appears to
be restoring the BP with the original FP content, not the original BP
content. When I merged the 32-bit and 64-bit code, I used the
corresponding code from the 64-bit flow, which I believe uses the
correct offset (BPOffset) for this operation.

llvm-svn: 188741
2013-08-20 03:12:23 +00:00
Andrew Kaylor e0c8f50f3e Marking MCJIT PIC tests as XFAIL on AArch64
llvm-svn: 188740
2013-08-20 01:50:50 +00:00