llvm-project

Author	SHA1	Message	Date
Devang Patel	63fe5697f4	Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] llvm-svn: 149142	2012-01-27 19:48:28 +00:00
Devang Patel	cf893a437e	Intel syntax: Robustify parsing of memory operand's displacement experssion. llvm-svn: 148737	2012-01-23 22:35:25 +00:00
Devang Patel	e660fdd953	Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] llvm-svn: 148721	2012-01-23 20:20:06 +00:00
Devang Patel	880bc1644b	Intel syntax: Parse segment registers. llvm-svn: 148712	2012-01-23 18:31:58 +00:00
Devang Patel	ce6a2ca8c8	Intel syntax: Robustify register parsing. llvm-svn: 148591	2012-01-20 22:32:05 +00:00
Devang Patel	de47cced25	Process instructions after match to select alternative encoding which may be more desirable. llvm-svn: 148431	2012-01-18 22:42:29 +00:00
Devang Patel	c9ed518792	Intel syntax: Fix parser match class to check memory operand size. llvm-svn: 148338	2012-01-17 21:48:03 +00:00
Devang Patel	a7143b6a2b	Intel syntax: Parse "BYTE PTR [RDX + RCX]" llvm-svn: 148334	2012-01-17 21:25:10 +00:00
Devang Patel	8b39be79ad	Intel syntax: Do not unncessarily create plus expression for memory operand displacement. llvm-svn: 148321	2012-01-17 19:08:07 +00:00
Devang Patel	a77c03be54	Intel syntax: Ignore mnemonic aliases. llvm-svn: 148316	2012-01-17 18:30:45 +00:00
Devang Patel	41b9ddeb7a	Intel syntax: Robustify memory operand parsing. llvm-svn: 148312	2012-01-17 18:00:18 +00:00
Devang Patel	5d85276e30	Add new test. llvm-svn: 148128	2012-01-13 18:45:31 +00:00

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