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Author SHA1 Message Date
Jim Grosbach bb07e73e0d Thumb parsing and encoding for SXTB and SXTH. 
llvm-svn: 138361
 2011-08-23 19:51:42 +00:00
Jim Grosbach 5cc338da67 Thumb parsing and encoding for SVC. 
llvm-svn: 138360
 2011-08-23 19:49:10 +00:00
Jim Grosbach d88404fbaa Thumb parsing and encoding for SUB. 
llvm-svn: 138359
 2011-08-23 19:45:45 +00:00
Nick Lewycky 4c8ff77f1b PerformSubCombine to work on integers larger than i128. Fixes a crasher. 
llvm-svn: 138354
 2011-08-23 19:01:24 +00:00
Jim Grosbach f1ca6a6df6 Thumb parsing and encoding for STRH. 
llvm-svn: 138352
 2011-08-23 18:56:20 +00:00
Jim Grosbach 635aa69a91 Thumb parsing and encoding for STRB. 
llvm-svn: 138349
 2011-08-23 18:43:06 +00:00
Jim Grosbach 505be75900 Thumb parsing and encoding for tSTRspi. 
llvm-svn: 138348
 2011-08-23 18:39:41 +00:00
Jim Grosbach 6e546e0725 Thumb parsing and encoding for STR. 
Not including tSTRspi.

llvm-svn: 138347
 2011-08-23 18:33:38 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Nadav Rotem 7d3effa389 Fix a typo in the test from the previous commit. 
llvm-svn: 138342
 2011-08-23 17:56:54 +00:00
Owen Anderson 924bcfc92f Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far. 
llvm-svn: 138341
 2011-08-23 17:51:38 +00:00
Nadav Rotem c78e6607b5 Address Duncan's CR request: 
1. Cleanup the tests in ConstantFolding.cpp
2. Implement isAllOnes for Constant, ConstantFP, ConstantVector

llvm-svn: 138340
 2011-08-23 17:48:43 +00:00
Owen Anderson 041dba6dec Fix two more instances of mis-matched operand names breaking disassembly. Found by randomized testing. 
llvm-svn: 138337
 2011-08-23 17:37:32 +00:00
Owen Anderson dcea63236e Port more assemble tests over to disassembly tests. 
llvm-svn: 138336
 2011-08-23 17:26:35 +00:00
Craig Topper 6612e35b0d Add support for breaking 256-bit v16i16 and v32i8 VSETCC into two 128-bit ones, avoiding sclarization. Add vex form of pcmpeqq and pcmpgtq. Fixes more cases for PR10712. 
llvm-svn: 138321
 2011-08-23 04:36:33 +00:00
Bruno Cardoso Lopes 2a3ffb5d97 Introduce a pass to insert vzeroupper instructions to avoid AVX to 
SSE transition penalty. The pass is enabled through the "x86-use-vzeroupper"
llc command line option. This is only the first step (very naive and
conservative one) to sketch out the idea, but proper DFA is coming next
to allow smarter decisions. Comments and ideas now and in further commits
will be very appreciated.

llvm-svn: 138317
 2011-08-23 01:14:17 +00:00
Jim Grosbach cc9d792ec1 Thumb parsing and encoding for SETEND. 
llvm-svn: 138312
 2011-08-22 23:58:02 +00:00
Jim Grosbach 3636be3c8f Thumb parsing and encoding for SBC. 
llvm-svn: 138311
 2011-08-22 23:55:58 +00:00
Jim Grosbach c3c32d9e09 Thumb parsing and encoding for RSB. 
llvm-svn: 138308
 2011-08-22 23:47:13 +00:00
Jim Grosbach 73661b8a37 Thumb parsing and encoding for ROR. 
llvm-svn: 138304
 2011-08-22 23:40:51 +00:00
Jim Grosbach a9d88df987 Thumb parsing and encoding for REV/REV16/REVSH. 
llvm-svn: 138303
 2011-08-22 23:39:25 +00:00
Owen Anderson 1346d79b4b t2SMLAD is a four-register instruction, not a three-register one. 
llvm-svn: 138301
 2011-08-22 23:31:45 +00:00
Owen Anderson f94b7b7d57 Correct operand naming of t2USAT16 to allow proper decoding. 
llvm-svn: 138300
 2011-08-22 23:27:47 +00:00
Owen Anderson 5e9989a920 Match operand naming to allow correct decoding of t2LDRSH_POST. 
llvm-svn: 138298
 2011-08-22 23:22:05 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Jim Grosbach 096423b6be Tidy up. Trailing whitespace. 
llvm-svn: 138293
 2011-08-22 23:13:54 +00:00
Owen Anderson a743409ec8 Provide a correct decoder hook for Thumb2 shifted registers. Found by randomized testing. 
llvm-svn: 138292
 2011-08-22 23:10:16 +00:00
Jim Grosbach 40da063178 Thumb parsing and encoding for PUSH. 
llvm-svn: 138290
 2011-08-22 23:05:11 +00:00
Jim Grosbach 5507203262 Fix think-o. 
llvm-svn: 138288
 2011-08-22 23:04:26 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Jim Grosbach 0869b900cc Thumb assembly parsing and encoding for POP. 
llvm-svn: 138286
 2011-08-22 23:00:19 +00:00
Owen Anderson 061738a680 Provide operand encoding information for half-precision VCVT instructions. Found by randomized testing. 
llvm-svn: 138273
 2011-08-22 21:34:00 +00:00
Bruno Cardoso Lopes 74f090d44c Add support for breaking 256-bit int VETCC into two 128-bit ones, 
avoding scalarization of the compare. Reduces code from 59 to 6
instructions. Fix PR10712.

llvm-svn: 138271
 2011-08-22 20:31:04 +00:00
Owen Anderson df698b032c Fix decoding of VMOVSRR and VMOVRRS, which account for the overwhelming majority of decoder crashes detected by randomized testing. 
llvm-svn: 138269
 2011-08-22 20:27:12 +00:00
Owen Anderson 721c3704da Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 
llvm-svn: 138255
 2011-08-22 18:42:13 +00:00
Owen Anderson ac92e77bb8 Correct writeback handling of duplicating VLD instructions. Discovered by randomized testing. 
llvm-svn: 138251
 2011-08-22 18:22:06 +00:00
Owen Anderson fe29fe431d Port another swathe of Thumb1 encoding tests over to decoding tests. 
llvm-svn: 138250
 2011-08-22 18:05:49 +00:00
Owen Anderson b49813206b Fix an incorrect shift when decoding SP-relative stores in Thumb1-mode. Add more tests. 
llvm-svn: 138246
 2011-08-22 17:56:58 +00:00
Jim Grosbach aa42847164 Thumb assembly parsing and encoding for ORR. 
llvm-svn: 138245
 2011-08-22 17:41:44 +00:00
Dan Gohman 56e1cef705 Constant pointers to objects don't need reference counting. 
llvm-svn: 138242
 2011-08-22 17:29:11 +00:00
Dan Gohman bce94fded8 Make a few tests slightly more strict. 
llvm-svn: 138241
 2011-08-22 17:27:02 +00:00
Duncan Sands b40654e21d Testcase for PR10663. 
llvm-svn: 138231
 2011-08-22 10:32:09 +00:00
Jim Grosbach bd16424f91 Fix AsmParser binary precedence for shift operators. 
rdar://9976729

llvm-svn: 138208
 2011-08-20 16:24:13 +00:00
Jim Grosbach 3322f02a03 Tidy up. Whitespace. 
llvm-svn: 138207
 2011-08-20 16:10:09 +00:00
Nadav Rotem ad4a70ad3e Add constant folding support for bitcasts of splat vectors to integers. 
llvm-svn: 138206
 2011-08-20 14:02:29 +00:00
Eric Christopher 6582dfa7c5 Remove remainder of migrated or obsolete tests from FrontendC and remove 
the empty directory.

llvm-svn: 138181
 2011-08-20 01:04:56 +00:00
Eric Christopher c19fd6eadc Remove migrated or obsolete tests. 
llvm-svn: 138176
 2011-08-20 00:49:30 +00:00
Eric Christopher 1efe3d9663 Remove obsolete or migrated tests. 
llvm-svn: 138173
 2011-08-20 00:38:20 +00:00
Chad Rosier d6641af80c With the fix in r138164: "Add <imp-def> operands to QQ and QQQQ stack loads." 
-verify-machineinstrs can be enabled for this test case.

llvm-svn: 138171
 2011-08-20 00:34:45 +00:00
Eric Christopher c2528a529a Remove obsoleted test. 
llvm-svn: 138170
 2011-08-20 00:26:30 +00:00
Eric Christopher a1124b45d2 Remove tests that were either migrated to clang or are obsolete. 
llvm-svn: 138168
 2011-08-20 00:25:42 +00:00
Eric Christopher 2f53dc2e05 Remove the rest of the files in FrontendC++ and the directory itself. 
All tests have been updated and migrated into clang or were obsolete.

llvm-svn: 138165
 2011-08-20 00:17:58 +00:00
Chad Rosier be7625161e VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. 
Therefore, rather then generate a pseudo instruction, which is later expanded,
generate the necessary instructions in place.

llvm-svn: 138163
 2011-08-20 00:17:25 +00:00
Eric Christopher 74cfab0fbe Remove migrated or obsolete tests. 
llvm-svn: 138156
 2011-08-20 00:08:36 +00:00
Eric Christopher a0b6bc5739 Remove migrated or obsolete tests. 
llvm-svn: 138149
 2011-08-19 23:41:50 +00:00
Devang Patel 59e27c5f12 Do not use named md nodes to track variables that are completely optimized. This does not scale while doing LTO with debug info. New approach is to include list of variables in the subprogram info directly. 
llvm-svn: 138145
 2011-08-19 23:28:12 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Eric Christopher 67edb5ef36 Remove obsolete test. 
llvm-svn: 138141
 2011-08-19 23:18:12 +00:00
Eric Christopher 2c16fef036 Remove migrated test. 
llvm-svn: 138140
 2011-08-19 23:18:10 +00:00
Jim Grosbach 8d77bb5f06 Use regex to remove false dependencies on register allocation. 
llvm-svn: 138137
 2011-08-19 23:10:31 +00:00
Eric Christopher 48f1599b03 Remove obsolete or migrated tests. 
llvm-svn: 138135
 2011-08-19 23:08:41 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Bruno Cardoso Lopes d126347f32 Re-write part of VEX encoding logic, to be more easy to read! Also fix 
a bug and add a testcase!

llvm-svn: 138123
 2011-08-19 22:27:29 +00:00
Eric Christopher 43d15b98d2 Remove tests migrated to clang. 
llvm-svn: 138121
 2011-08-19 22:26:09 +00:00
Eric Christopher 1e1cbc5f65 Remove previously migrated test. 
llvm-svn: 138120
 2011-08-19 22:26:06 +00:00
Jim Grosbach 066e9ec1e4 Update tests. 
llvm-svn: 138116
 2011-08-19 22:19:48 +00:00
Eric Christopher 58ce352d32 Remove tests migrated to clang or are unnecessary. 
llvm-svn: 138115
 2011-08-19 22:17:09 +00:00
Jim Grosbach fd4de3aeff Thumb assembly parsing and encoding for MVN. 
llvm-svn: 138109
 2011-08-19 22:09:23 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Eric Christopher 029529369b Remove this test. The feature and test have already been migrated to clang. 
llvm-svn: 138101
 2011-08-19 21:51:41 +00:00
Eric Christopher 772aa6c82e Remove tests migrated to clang. 
llvm-svn: 138100
 2011-08-19 21:51:39 +00:00
Eric Christopher 981c15ef76 Remove 2009-09-04-modify-crash.cpp as clang doesn't support 32-bit kext. 
llvm-svn: 138087
 2011-08-19 21:21:28 +00:00
Eric Christopher 05927b0c90 Remove migrated tests. 
llvm-svn: 138086
 2011-08-19 21:21:26 +00:00
Eric Christopher e8ad105202 Remove migrated test. 
llvm-svn: 138085
 2011-08-19 21:21:24 +00:00
Eric Christopher 526162d18e Remove this test. There are other, duplicates, in the clang test suite. 
llvm-svn: 138084
 2011-08-19 21:21:21 +00:00
Eric Christopher 8af4e41734 Add file. 
llvm-svn: 138083
 2011-08-19 21:21:20 +00:00
Eric Christopher 810ed3a7c3 Move 2010-03-22-empty-baseclass.cpp from a frontend+opt test to just 
an opt test.

llvm-svn: 138082
 2011-08-19 21:21:14 +00:00
Jim Grosbach d07e104844 Add FIXME. 
llvm-svn: 138077
 2011-08-19 20:48:54 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach 1eb6eb0955 Thumb assembly parsing and encoding for LSR. 
llvm-svn: 138065
 2011-08-19 19:34:22 +00:00
Jim Grosbach 3245520ade Thumb assembly parsing and encoding for LSL(register). 
llvm-svn: 138064
 2011-08-19 19:30:58 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 7c4739da3c Thumb assembly parsing and encoding for LDRSB and LDRSH. 
llvm-svn: 138061
 2011-08-19 19:17:58 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach 106281f329 Thumb assembly parsing and encoding for LDR(register). 
llvm-svn: 138056
 2011-08-19 18:35:06 +00:00
Jim Grosbach 181d2f92b5 Thumb assembly parsing and encoding for LDR(literal). 
llvm-svn: 138052
 2011-08-19 18:20:48 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Craig Topper ba6c2a52c7 Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler 
llvm-svn: 138034
 2011-08-19 05:28:50 +00:00
Jakob Stoklund Olesen 90b6018c8f Add test case for r138018. 
llvm-svn: 138033
 2011-08-19 04:30:24 +00:00
Bruno Cardoso Lopes 22241acc29 Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the 
implementation!

llvm-svn: 138029
 2011-08-19 02:23:56 +00:00
Dan Gohman b38940135b Track a retain+release nesting level independently of the 
known-incremented level, because the two concepts can be used
to prove the saftey of a retain+release removal in different
ways.

llvm-svn: 138016
 2011-08-19 00:26:36 +00:00
Akira Hatanaka fb4161ae88 Use subword loads instead of a 4-byte load when the size of a structure (or a 
piece of it) that is being passed by value is smaller than a word.

llvm-svn: 138007
 2011-08-18 23:39:37 +00:00
Owen Anderson 96b7ad2e17 STC2L_POST and STC2L_POST should be handled the same as STCL_POST/LDC_POST for the purposes of decoding all operands except the predicate. 
Found by randomized testing.

llvm-svn: 138003
 2011-08-18 22:47:44 +00:00
Owen Anderson 192a760b54 Fix the decoding of RFE instruction. RFEs have the load bit set, while SRSs have it unset. 
llvm-svn: 138000
 2011-08-18 22:31:17 +00:00
Owen Anderson 67d6f11974 Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions. 
Fixes a large class of disassembler crashes found by randomized testing.

llvm-svn: 137995
 2011-08-18 22:11:02 +00:00
Ivan Krasin d7cbd4c518 FastISel: avoid function calls between the materialization of the constant and its use. 
llvm-svn: 137993
 2011-08-18 22:06:10 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Owen Anderson 627021d7c0 More Thumb1 decoding tests. 
llvm-svn: 137974
 2011-08-18 20:05:06 +00:00
Devang Patel 0071f8a48e Add another test. 
llvm-svn: 137969
 2011-08-18 18:50:25 +00:00
Devang Patel f907e78b78 Add test to check type uniquing. 
llvm-svn: 137968
 2011-08-18 18:40:49 +00:00
Jim Grosbach 6cb336cb09 Thumb assembly parsing and encoding for EOR. 
llvm-svn: 137964
 2011-08-18 18:10:38 +00:00
Jim Grosbach 4f240a1fd5 Thumb assembly parsing and encoding for CMP. 
llvm-svn: 137963
 2011-08-18 18:08:29 +00:00
James Molloy 9f9371ccb3 Test commit; adding test for invalid LDRD which was part of the patch for r137647 but seemingly didn't get svn add'ed. 
llvm-svn: 137960
 2011-08-18 18:03:02 +00:00
Jim Grosbach 47bf39d921 Thumb assembly parsing and encoding test for CMN. 
llvm-svn: 137957
 2011-08-18 17:55:03 +00:00
Owen Anderson ec3884c50a Port over BL/BLX to disassembly tests. 
llvm-svn: 137954
 2011-08-18 17:43:52 +00:00
Jim Grosbach 0081879ee7 ARM assembly parsing and encoding test for BX/BLX (register). 
llvm-svn: 137949
 2011-08-18 17:02:28 +00:00
Jim Grosbach 8b7158e557 ARM assembly parsing and encoding test for BL/BLX (immediate). 
llvm-svn: 137948
 2011-08-18 17:00:09 +00:00
Richard Osborne 56f3b70225 Add intrinsics for SETEV, GETED, GETET. 
llvm-svn: 137938
 2011-08-18 13:00:48 +00:00
Bruno Cardoso Lopes 3c7d6eb64c Cleanup vector logical ops in AVX and add use int versions for simple 
v2i64

llvm-svn: 137919
 2011-08-18 02:11:34 +00:00
Owen Anderson a90896397b Port new Thumb1 encoding tests over to decoding tests. 
llvm-svn: 137902
 2011-08-17 23:37:33 +00:00
Jim Grosbach 1b43828958 ARM assembly parsing and encoding test for BKPT. 
llvm-svn: 137898
 2011-08-17 23:11:13 +00:00
Jim Grosbach e3bdcd0ea8 ARM assembly parsing and encoding test for BIC. 
llvm-svn: 137895
 2011-08-17 23:00:53 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Eli Friedman 9a468153e1 Atomic load/store handling for the passes using memdep (GVN, DSE, memcpyopt). 
llvm-svn: 137888
 2011-08-17 22:22:24 +00:00
Bruno Cardoso Lopes 1a87fcb9ba Fix PR10688. Add support for spliting 256-bit vector shifts when the 
shift amount is variable

llvm-svn: 137885
 2011-08-17 22:12:20 +00:00
Jim Grosbach e2a0404a69 Thumb assembly parsing and encoding for ADR. 
llvm-svn: 137864
 2011-08-17 20:37:40 +00:00
Jim Grosbach e2d152016f Add a couple of FIXMEs. 
llvm-svn: 137861
 2011-08-17 20:35:57 +00:00
Devang Patel 35ea5cfd46 Fix test case. 
llvm-svn: 137847
 2011-08-17 18:48:28 +00:00
Devang Patel ae2848ed69 Remove superficial test. 
llvm-svn: 137846
 2011-08-17 18:39:13 +00:00
Devang Patel 3fee10b7d2 Robustify test. 
llvm-svn: 137845
 2011-08-17 18:38:44 +00:00
Owen Anderson d40d838cc4 Start building a Thumb1 decoding test file based on the Thumb1 parsing/encoding test file. 
llvm-svn: 137840
 2011-08-17 18:21:36 +00:00
Eli Friedman d7749be2d7 Silly mistake from r137777; restore significant isStructTy() checks. While here, be a bit more defensive 
with unknown instructions.

Fixes PR10687.

llvm-svn: 137836
 2011-08-17 18:10:43 +00:00
Jim Grosbach 80636b48c0 Thumb assembly parsing and encoding for ADC(register) instruction. 
llvm-svn: 137833
 2011-08-17 17:55:28 +00:00
Jim Grosbach a806eebe13 Add missing '@' delimiter. 
llvm-svn: 137832
 2011-08-17 17:46:01 +00:00
Owen Anderson a4043c4b32 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Bruno Cardoso Lopes be5e987379 Introduce matching patterns for vbroadcast AVX instruction. The idea is to 
match splats in the form (splat (scalar_to_vector (load ...))) whenever
the load can be folded. All the logic and instruction emission is
working but because of PR8156, there are no ways to match loads, cause
they can never be folded for splats. Thus, the tests are XFAILed, but
I've tested and exercised all the logic using a relaxed version for
checking the foldable loads, as if the bug was already fixed. This
should work out of the box once PR8156 gets fixed since MayFoldLoad will
work as expected.

llvm-svn: 137810
 2011-08-17 02:29:19 +00:00
Bruno Cardoso Lopes 3400825b41 Update test to not use the scalar type to splat from a load 
llvm-svn: 137809
 2011-08-17 02:29:15 +00:00
Bruno Cardoso Lopes ed786a346e Now that we have a canonical way to handle 256-bit splats: 
vinsertf128 $1 + vpermilps $0, remove the old code that used to first
do the splat in a 128-bit vector and then insert it into a larger one.
This is better because the handling code gets simpler and also makes a
better room for the upcoming vbroadcast!

llvm-svn: 137807
 2011-08-17 02:29:10 +00:00
Akira Hatanaka 5360f88355 Add support for ext and ins. 
llvm-svn: 137804
 2011-08-17 02:05:42 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Eli Friedman e1df253200 An additional atomic test; related to r137662. 
llvm-svn: 137786
 2011-08-16 23:29:17 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Eli Friedman 0793eb4c46 A bunch of misc fixes to SCCPSolver::ResolvedUndefsIn, including a fix to stop 
making random bad assumptions about instructions which are not explicitly listed.  

Includes fix for rdar://9956541, a version of "undef ^ undef should return
0 because it's easier than arguing with users".

llvm-svn: 137777
 2011-08-16 22:06:31 +00:00
Eric Christopher d56ba41bc3 Remove tests that have been obsoleted or migrated to clang/optimizer tests. 
llvm-svn: 137775
 2011-08-16 21:46:25 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Eli Friedman 56f2f21254 Minor bug in SCCP found by inspection. (I don't think it's possible to hit this with a normal pass pipeline, but fixing for completeness.) 
llvm-svn: 137755
 2011-08-16 21:12:35 +00:00
Jim Grosbach 2c21bf4b43 Add testcase for r137746. 
llvm-svn: 137754
 2011-08-16 21:11:21 +00:00
Jim Grosbach d3ad0aa413 Tidy up formatting. 
llvm-svn: 137747
 2011-08-16 20:55:41 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Bruno Cardoso Lopes 2e99f1b3aa Instead of always leaving the work to the generic legalizer when 
there is no support for native 256-bit shuffles, be more smart in some
cases, for example, when you can extract specific 128-bit parts and use
regular 128-bit shuffles for them. Example:

For this shuffle:
  shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32>
                <i32 1, i32 0, i32 7, i32 6>

This was expanded to:
  vextractf128  $1, %ymm1, %xmm2
  vpextrq $0, %xmm2, %rax
  vmovd %rax, %xmm1
  vpextrq $1, %xmm2, %rax
  vmovd %rax, %xmm2
  vpunpcklqdq %xmm1, %xmm2, %xmm1
  vpextrq $0, %xmm0, %rax
  vmovd %rax, %xmm2
  vpextrq $1, %xmm0, %rax
  vmovd %rax, %xmm0
  vpunpcklqdq %xmm2, %xmm0, %xmm0
  vinsertf128 $1, %xmm1, %ymm0, %ymm0
  ret

Now we get:
  vshufpd $1, %xmm0, %xmm0, %xmm0
  vextractf128  $1, %ymm1, %xmm1
  vshufpd $1, %xmm1, %xmm1, %xmm1
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

llvm-svn: 137733
 2011-08-16 18:21:54 +00:00
Akira Hatanaka 7d7bec5acf Add test case for r137711. 
llvm-svn: 137725
 2011-08-16 17:32:01 +00:00
Jim Grosbach 45e50d8a0b ARM .align NOP padding uses different encoding pre-ARMv6. 
Patch by Kristof Beyls and James Malloy.

llvm-svn: 137723
 2011-08-16 17:06:20 +00:00
Akira Hatanaka 2263c10946 Fix handling of double precision loads and stores when Mips1 is targeted. 
Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711
 2011-08-16 03:51:51 +00:00
Eli Friedman ac992afd93 Fix test. 
llvm-svn: 137703
 2011-08-16 01:42:56 +00:00
Eli Friedman a917d4f9b4 Revert a bit of r137667; the logic in question can safely handle atomic load/store. 
llvm-svn: 137702
 2011-08-16 01:28:22 +00:00
Eric Christopher 5403862ab7 Migrate this test from llvm/test/FrontendC++/ptr-to-method-devirt.cpp and 
FileCheckize. It is more properly an optimizer test.

llvm-svn: 137700
 2011-08-16 01:17:17 +00:00
Eli Friedman 0ffdf2ea0b Update SimplifyCFG for atomic operations. 
This commit includes a mention of the landingpad instruction, but it's not
changing the behavior around it.  I think the current behavior is correct,
though.  Bill, can you double-check that?

llvm-svn: 137691
 2011-08-15 23:59:28 +00:00
Eli Friedman 01a67111d1 Add comments and test for atomic load/store and mem2reg. 
llvm-svn: 137690
 2011-08-15 23:55:52 +00:00
Owen Anderson 53440984b3 Add a test file for Thumb2 NEON. 
llvm-svn: 137687
 2011-08-15 23:42:20 +00:00
Bruno Cardoso Lopes 67005029bc Reorder declarations of vmovmskp* and also put the necessary AVX 
predicate and TB encoding fields. This fix the encoding for the
attached testcase. This fixes PR10625.

llvm-svn: 137684
 2011-08-15 23:36:45 +00:00
Eli Friedman 8bc586e770 Update instcombine for atomic load/store. 
llvm-svn: 137664
 2011-08-15 22:09:40 +00:00
Bruno Cardoso Lopes cbe7feeab9 Fix PR10656. It's only profitable to use 128-bit inserts and extracts 
when AVX mode is one. Otherwise is just more work for the type
legalizer.

llvm-svn: 137661
 2011-08-15 21:45:54 +00:00
Owen Anderson 5286bd2d01 Add some more comprehensive VFP decoding tests. 
llvm-svn: 137657
 2011-08-15 21:29:01 +00:00
Eric Christopher 8c5f3f7624 Fix this test to avoid leaving a temporary file behind. 
llvm-svn: 137651
 2011-08-15 20:55:03 +00:00
Eli Friedman 91386c7be4 Atomic load/store support in LICM. 
llvm-svn: 137648
 2011-08-15 20:52:09 +00:00
Owen Anderson 1d5d2cac8c Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Eric Christopher 990dd3d0fb Add an ipsccp test. Migrated from test/FrontendC++. 
llvm-svn: 137646
 2011-08-15 20:50:36 +00:00
Owen Anderson 944f4923a4 Add a test for Thumb1 LDRSH decoding. 
llvm-svn: 137645
 2011-08-15 20:15:43 +00:00
Owen Anderson f746b0ec53 Add testcase for STRH. Patch by James Molloy. 
llvm-svn: 137644
 2011-08-15 20:12:03 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy. 
llvm-svn: 137641
 2011-08-15 20:08:25 +00:00
Owen Anderson 3157f2eebe Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy. 
llvm-svn: 137636
 2011-08-15 19:00:06 +00:00
Owen Anderson b9d82f411c Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Nick Lewycky 746e317953 This transform is not safe. Thanks to Eli for pointing that out! 
llvm-svn: 137575
 2011-08-14 04:51:49 +00:00
Nick Lewycky ae13df60a6 Don't attempt to add 'nsw' when intermediate instructions had no such guarantee. 
llvm-svn: 137572
 2011-08-14 03:41:33 +00:00
Nick Lewycky de49278c26 Teach instcombine to preserve the nsw bit by doing an after-the-fact analysis 
when combining add and sub instructions. Patch by Pranav Bhandarkar!

llvm-svn: 137570
 2011-08-14 01:45:19 +00:00
Eli Friedman 9f56acc124 Fix test. 
llvm-svn: 137556
 2011-08-13 17:06:34 +00:00
Bob Wilson d1de7764be Expand VMOVQQQQ pseudo instructions. 
Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

llvm-svn: 137551
 2011-08-13 05:14:55 +00:00
Eli Friedman 02e737b08e Move "atomic" and "volatile" designations on instructions after the opcode 
of the instruction.

Note that this change affects the existing non-atomic load and store
instructions; the parser now accepts both forms, and the change is noted
in the release notes.

llvm-svn: 137527
 2011-08-12 22:50:01 +00:00
Bruno Cardoso Lopes f15dfe5818 The VPERM2F128 is a AVX instruction which permutes between two 256-bit 
vectors. It operates on 128-bit elements instead of regular scalar
types. Recognize shuffles that are suitable for VPERM2F128 and teach
the x86 legalizer how to handle them.

llvm-svn: 137519
 2011-08-12 21:48:26 +00:00
Akira Hatanaka 2fcc1cfdce Define unaligned load and store. 
llvm-svn: 137515
 2011-08-12 21:30:06 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson ed6d3e813e Port over the basic ARM encodings test file to a decoding test file. Greatly increases our test coverage of basic ARM-mode instructions. 
llvm-svn: 137495
 2011-08-12 19:42:45 +00:00
Akira Hatanaka 2f6b944f56 Test case for 137484 
llvm-svn: 137486
 2011-08-12 18:12:06 +00:00
Jim Grosbach d1b60f7a6d Tidy up formatting. 
llvm-svn: 137471
 2011-08-12 17:43:31 +00:00
Jim Grosbach 234317d12a Tidy up formatting. 
llvm-svn: 137464
 2011-08-12 17:01:02 +00:00
Benjamin Kramer 91ea511436 MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does. 
llvm-svn: 137414
 2011-08-12 01:51:29 +00:00
Dan Gohman 10a18d55ce Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result 
is returned through a bitcast.

llvm-svn: 137402
 2011-08-12 00:36:31 +00:00
Dan Gohman 121302772d Don't let arbitrary calls disrupt nested retain+release pairs if 
the retains and releases all use the same SSA pointer value.

Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.

llvm-svn: 137399
 2011-08-12 00:26:31 +00:00
Jim Grosbach 1978ddf769 Clean up formatting a bit. 
llvm-svn: 137393
 2011-08-11 23:57:17 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Andrew Trick 2d8494a030 A slew of unit tests for the recent LoopInfo::updateUnloop feature 
checked in at r137276 and r137341.

llvm-svn: 137385
 2011-08-11 23:38:09 +00:00
Andrew Trick 2b6860f0a1 Allow loop unrolling to get known trip counts from ScalarEvolution. 
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.

This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.

llvm-svn: 137384
 2011-08-11 23:36:16 +00:00
Akira Hatanaka 79d60d0e94 Enclose directive .cprestore with .set macro and nomacro to silence assembler 
warning. 

llvm-svn: 137378
 2011-08-11 22:42:31 +00:00
Jim Grosbach aa07cb6a98 Fix tests per now-correct encoding as of r137371. 
llvm-svn: 137376
 2011-08-11 22:31:48 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Bruno Cardoso Lopes 8fbf023c9b Add a dag combine to xform 256-bit shuffles into simple vector 
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.

llvm-svn: 137362
 2011-08-11 21:50:44 +00:00
Bruno Cardoso Lopes 9eb3762e08 Fix the test added by Nadav in r137308. Make it more strict: 
1) check for the "v" version of movaps
2) add a couple of CHECK-NOT to guarantee the behavior
3) move to a more appropriate test file

llvm-svn: 137361
 2011-08-11 21:50:35 +00:00
Jim Grosbach 7db3bfbd45 ARM STRHT assembly parsing and encoding. 
llvm-svn: 137358
 2011-08-11 21:39:41 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Owen Anderson 3a850f28d0 Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson 887c0b1358 Improve operand validation for Thumb2 addressing modes. 
llvm-svn: 137344
 2011-08-11 20:40:40 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Jim Grosbach d0767f37c1 Add FIXME. 
llvm-svn: 137336
 2011-08-11 19:43:42 +00:00
Jim Grosbach 295788756d ARM STRB assembly parsing and encoding tests. 
llvm-svn: 137335
 2011-08-11 19:42:58 +00:00
Jim Grosbach 14a4164206 Fix a copy/paste error so that LDRB(register) actually gets tested. 
llvm-svn: 137333
 2011-08-11 19:34:23 +00:00
Jim Grosbach 06b7f0c901 ARM STR(register) assembly parsing and encoding tests. 
llvm-svn: 137332
 2011-08-11 19:26:17 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Owen Anderson 3477f2cea5 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Bruno Cardoso Lopes 043c820800 Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict. 
llvm-svn: 137324
 2011-08-11 18:59:13 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson e33c95d39b Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me. 
llvm-svn: 137322
 2011-08-11 18:41:59 +00:00
Owen Anderson ed25385227 Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Nadav Rotem 1542d5a00a [AVX] If the data which is going to be saved is already in two XMM registers 
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.

Before:
                vinsertf128         $1, %xmm3, %ymm0, %ymm3
                vinsertf128         $0, %xmm1, %ymm3, %ymm1
                vmovaps              %ymm1, 416(%rsp)

After:
                vmovaps              %xmm3, 416+16(%rsp)
                vmovaps              %xmm1, 416(%rsp)

llvm-svn: 137308
 2011-08-11 16:41:21 +00:00
Chris Lattner 5a2c70cc8f add missing colon, thanks peter. 
llvm-svn: 137306
 2011-08-11 16:15:10 +00:00
Chris Lattner 96710b4308 fix PR10605 / rdar://9930964 by adding a pretty scary missed check. 
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
 2011-08-11 06:26:54 +00:00
Bruno Cardoso Lopes a2d8bb97b9 Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing 
infinite recursive calls in legalize. Fix PR10562

llvm-svn: 137296
 2011-08-11 02:49:44 +00:00
Bruno Cardoso Lopes 572c9aaf53 Use the splat index to generate the desired shuffle. Otherwise we 
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.

llvm-svn: 137295
 2011-08-11 02:49:41 +00:00
Eli Friedman 3ae39f8ad1 Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2). 
Fixes PR9693.

llvm-svn: 137292
 2011-08-11 01:48:05 +00:00
Jim Grosbach 94ba2cba6e ARM tests for LDRSHT assembly parsing and encoding. 
llvm-svn: 137274
 2011-08-10 23:18:30 +00:00
Jim Grosbach a6ab52bf9f ARM tests for LDRSH assembly parsing and encoding. 
llvm-svn: 137272
 2011-08-10 23:12:25 +00:00
Jim Grosbach 2953404723 ARM tests for LDRSBT assembly parsing and encoding. 
llvm-svn: 137271
 2011-08-10 23:08:56 +00:00
Jim Grosbach c11bbf3bda ARM tests for LDRSB assembly parsing and encoding. 
llvm-svn: 137270
 2011-08-10 23:06:44 +00:00
Jim Grosbach 35cdf36c32 Add FIXME. 
llvm-svn: 137265
 2011-08-10 22:56:43 +00:00
Jim Grosbach 5e0c9711f2 ARM tests for LDRHT assembly parsing and encoding. 
llvm-svn: 137263
 2011-08-10 22:55:38 +00:00
NAKAMURA Takumi 504769fc2f test/CodeGen/X86/opt-shuff-tstore.ll: Add explicit -mtriple=x86_64-linux. 
llvm-svn: 137262
 2011-08-10 22:52:48 +00:00
Jim Grosbach 7cd4253cc3 ARM tests for LDRH(register) assembly parsing and encoding. 
llvm-svn: 137261
 2011-08-10 22:45:42 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach ae1b002fa3 Add FIXME 
llvm-svn: 137258
 2011-08-10 22:20:38 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Devang Patel 37a62058fe While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases. 
llvm-svn: 137250
 2011-08-10 21:25:34 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Nadav Rotem d2b071f562 Fix the test. Add cpu target. 
llvm-svn: 137241
 2011-08-10 19:49:19 +00:00
Nadav Rotem 410a11fe82 When performing a truncating store, it is sometimes possible to rearrange the 
data in-register prior to saving to memory.  When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.

llvm-svn: 137238
 2011-08-10 19:30:14 +00:00
Owen Anderson c86a5bd219 Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Bruno Cardoso Lopes 3ff111c12d The following X86 pattern is incorrect: 
def : Pat<(X86Movss VR128:$src1,
                   (bc_v4i32 (v2i64 (load addr:$src2)))),
          (MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.

llvm-svn: 137227
 2011-08-10 17:45:17 +00:00
Rafael Espindola 36a3abc671 Add support for the R and Q constraints. 
llvm-svn: 137217
 2011-08-10 16:26:42 +00:00
Andrew Trick 4d0040baf8 Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534. 
llvm-svn: 137203
 2011-08-10 04:29:49 +00:00
Bruno Cardoso Lopes 278ffd7d8e Fix a bug in vpermilps mask checking. Fix PR10560 
llvm-svn: 137194
 2011-08-10 01:54:17 +00:00
Peter Collingbourne c6bd551db0 Remove the build_unwind function from the OCaml bindings. 
llvm-svn: 137193
 2011-08-10 01:10:17 +00:00
Andrew Trick b72bbe2a92 Fix the LoopUnroller to handle nontrivial loops and partial unrolling. 
These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.

llvm-svn: 137190
 2011-08-10 00:28:10 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
llvm-svn: 137189
 2011-08-10 00:03:03 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands. 
llvm-svn: 137180
 2011-08-09 23:33:27 +00:00
Bruno Cardoso Lopes 72323966c8 Add 256-bit support for v8i32, v4i64 and v4f64 ISD::SELECT. Fix PR10556 
llvm-svn: 137179
 2011-08-09 23:27:13 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions. 
llvm-svn: 137176
 2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions. 
llvm-svn: 137172
 2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
llvm-svn: 137168
 2011-08-09 22:48:45 +00:00
Bruno Cardoso Lopes fc481959d2 Add v16i16 and v32i8 store patterns 
llvm-svn: 137166
 2011-08-09 22:39:53 +00:00
Bruno Cardoso Lopes 6963062a99 Use fp unpack instructions to unpack int types. Until we have AVX2, this 
is the best we can do for these patterns. This fix PR10554.

llvm-svn: 137161
 2011-08-09 22:18:37 +00:00
Eli Friedman 4ef2426b87 Fix a couple ridiculous copy-paste errors. rdar://9914773 . 
llvm-svn: 137160
 2011-08-09 22:17:39 +00:00
Benjamin Kramer 406dc1755f ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
 2011-08-09 22:02:50 +00:00
Owen Anderson 7a2401dbf0 Tighten Thumb1 branch predicate decoding. 
llvm-svn: 137146
 2011-08-09 21:07:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Bill Wendling d7f41b7f66 Revert r137134. It breaks some code as Eli pointed out. 
llvm-svn: 137135
 2011-08-09 18:56:35 +00:00
Bill Wendling 84ec8f65d1 Print out the variable declaration only if it is a declaration. Otherwise, a 
'static' variable will be emitted twice.
PR10081

llvm-svn: 137134
 2011-08-09 18:31:50 +00:00
Jakob Stoklund Olesen 53910d6aae Inflate register classes after coalescing. 
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class.  Examples are:

  x86: GR32_ABCD:sub_8bit_hi -> GR32
  arm: DPR_VFP2:ssub0 -> DPR

Recompute the register class of any virtual registers that are used by
less instructions after coalescing.

This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:

  vadd.f32  d16, d1, d0
  vcvt.s32.f32  d0, d16

The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.

llvm-svn: 137133
 2011-08-09 18:19:41 +00:00
Bruno Cardoso Lopes bed48dc8ff Reapply a more appropriate solution than in r137114. AVX supports 
v4f64 = sitofp v4i32. This fix PR10559.
Also add support for v4i32 = fptosi v4f64.

llvm-svn: 137128
 2011-08-09 17:39:13 +00:00
Bruno Cardoso Lopes 24dd1d4a27 Revert r137114 
llvm-svn: 137127
 2011-08-09 17:39:01 +00:00
Justin Holewinski db05c2b963 PTX: Add initial support for device function calls 
- Calls are supported on SM 2.0+ for function with no return values

llvm-svn: 137125
 2011-08-09 17:36:31 +00:00
Bruno Cardoso Lopes ad3453cf2d Handle sitofp between v4f64 <- v4i32. Fix PR10559 
llvm-svn: 137114
 2011-08-09 05:48:01 +00:00
Bruno Cardoso Lopes 1155b1eafa Add support for avx vector fextend 
llvm-svn: 137105
 2011-08-09 03:04:29 +00:00
Bruno Cardoso Lopes 337a7fdb13 Rename and tidy up tests 
llvm-svn: 137103
 2011-08-09 03:04:23 +00:00
Bruno Cardoso Lopes 2fc107365b Add two patterns to match special vmovss and vmovsd cases. Also fix 
the patterns already there to be more strict regarding the predicate.
This fixes PR10558

llvm-svn: 137100
 2011-08-09 01:43:09 +00:00
Bruno Cardoso Lopes af6a85484c Make LowerVSETCC aware of AVX types and add patterns to match them. 
llvm-svn: 137090
 2011-08-09 00:46:57 +00:00
Dan Gohman b24a1d29cb Tidy up these testcases to look more like real code does. 
llvm-svn: 137085
 2011-08-09 00:33:11 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction. 
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
 2011-08-08 23:28:47 +00:00
Jim Grosbach 5838c0c47e ARM parsing and encoding for LDRB instruction. 
llvm-svn: 137071
 2011-08-08 22:37:06 +00:00
Jim Grosbach f6dbc3a57c Add FIXME. 
llvm-svn: 137070
 2011-08-08 22:11:33 +00:00
Bruno Cardoso Lopes c96953c12a Add support for several vector shifts operations while in AVX mode. Fix PR10581 
llvm-svn: 137067
 2011-08-08 21:31:08 +00:00
Eli Friedman a27da98921 Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611. 
llvm-svn: 137061
 2011-08-08 19:49:37 +00:00
Jakob Stoklund Olesen 4f0ace5674 Don't clobber pending ST regs when FP regs are killed. 
X86FloatingPoint keeps track of pending ST registers for an upcoming
inline asm instruction with fixed stack register constraints.  It does
this by remembering which FP register holds the value that should appear
at a fixed stack position for the inline asm.

When that FP register is killed before the inline asm, make sure to
duplicate it to a scratch register, so the ST register still has a live
FP reference.

This could happen when the same FP register was copied to two ST
registers, or when a spill instruction is inserted between the ST copy
and the inline asm.

This fixes PR10602.

llvm-svn: 137050
 2011-08-08 17:15:43 +00:00
Andrew Trick 6d45a01b67 Made SCEV's UDiv expressions more canonical. When dividing a 
recurrence, the initial values low bits can sometimes be ignored.

To take advantage of this, added FoldIVUser to IndVarSimplify to fold
an IV operand into a udiv/lshr if the operator doesn't affect the
result.

-indvars -disable-iv-rewrite now transforms

i = phi i4
i1 = i0 + 1
idx = i1 >> (2 or more)
i4 = i + 4

into

i = phi i4
idx = i0 >> ...
i4 = i + 4

llvm-svn: 137013
 2011-08-06 07:00:37 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00
Jim Grosbach 0f2dd284e9 Add ARM LDR parsing tests. 
llvm-svn: 136977
 2011-08-05 20:33:39 +00:00
Devang Patel c0174048a4 We need to map DebugLoc. It leads to Fuction * (through subprogram entry node) which should be appropriately mapped. 
llvm-svn: 136910
 2011-08-04 20:02:18 +00:00
Devang Patel 6ddbb2e277 Linke NamedMDNodes after linking global values as comment suggests. 
llvm-svn: 136909
 2011-08-04 19:44:28 +00:00
Rafael Espindola 77dde89b90 Fix the bitwidth of the remaining fields. 
llvm-svn: 136884
 2011-08-04 17:00:11 +00:00
Rafael Espindola 9bc32a96be print st_shndx with the correct number of bits. 
llvm-svn: 136880
 2011-08-04 15:50:13 +00:00
Rafael Espindola 9528995e3f print st_other with the correct number of bits. 
llvm-svn: 136877
 2011-08-04 15:38:19 +00:00
Rafael Espindola 96df560ce1 print st_type with the correct number of bits. 
llvm-svn: 136875
 2011-08-04 15:24:00 +00:00
Rafael Espindola 79ef75dc49 Print st_bind with the correct number of bits. 
llvm-svn: 136874
 2011-08-04 15:10:35 +00:00
Rafael Espindola 1848231ad1 Print r_sym with the correct number of bits. 
llvm-svn: 136873
 2011-08-04 14:48:27 +00:00
Rafael Espindola 260af5cef6 Print r_type with the correct number of bits. 
llvm-svn: 136872
 2011-08-04 14:39:30 +00:00
Rafael Espindola 1b282e7e49 Another counter goes decimal. 
llvm-svn: 136871
 2011-08-04 14:27:46 +00:00
Rafael Espindola 65c559c5fb Change anther counter to decimal. 
llvm-svn: 136870
 2011-08-04 14:01:03 +00:00
Rafael Espindola cad9e7f094 Don't print a counter in hex. 
llvm-svn: 136869
 2011-08-04 13:39:15 +00:00
Rafael Espindola 69c67d3b18 Print all the bits in the addend. 
llvm-svn: 136867
 2011-08-04 13:00:24 +00:00
Jason W Kim e4df09f7ba Fix http://llvm.org/bugs/show_bug.cgi?id=10568 
Move the reloc size assert into AsmBackend - where it is more apropos.

llvm-svn: 136855
 2011-08-04 00:38:45 +00:00
Bill Wendling e234f6ae0c Only access both operands of an INSERT_SUBVECTOR if it is an INSERT_SUBVECTOR. 
Fixes PR10527.

llvm-svn: 136853
 2011-08-04 00:32:58 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
 2011-08-03 23:50:40 +00:00
Benjamin Kramer 3c7e9ee480 Remove underscore that's breaking linux buildbots. 
llvm-svn: 136833
 2011-08-03 23:13:01 +00:00
Jakub Staszak 15e5b742ad Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics. 
llvm-svn: 136826
 2011-08-03 22:34:43 +00:00
Bill Wendling 2d3138c112 Remove the LowerSetJmp pass. It wasn't used effectively by any of the targets. 
This is some of my original LLVM code. *wipes tear*

llvm-svn: 136821
 2011-08-03 22:18:20 +00:00
Andrew Trick bf69d03382 SCEV: Use AssertingVH to catch dangling BasicBlock* when passes forget 
to notify SCEV of a change. Add forgetLoop in a couple of those places.

llvm-svn: 136797
 2011-08-03 18:32:11 +00:00
Jakob Stoklund Olesen da618420ee Handle IMPLICIT_DEF instructions in X86FloatingPoint. 
This fixes PR10575.

llvm-svn: 136787
 2011-08-03 16:33:19 +00:00
Chris Lattner 5b82a0ac0c fix PR10286, a problem with the .ll printer handling block addresses that are out-of-scope. 
llvm-svn: 136768
 2011-08-03 06:15:41 +00:00
Devang Patel dc9cbaaf23 Use byte offset, instead of element number, to access merged global. 
llvm-svn: 136759
 2011-08-03 01:25:46 +00:00
Nick Lewycky 50f4966ceb Fix logical error when detecting lifetime intrinsics. 
Don't replace a gep/bitcast with 'undef' because that will form a "free(undef)"
which in turn means "unreachable". What we wanted was a no-op. Instead, analyze
the whole tree and look for all the instructions we need to delete first, then
delete them second, not relying on the use_list to stay consistent.

llvm-svn: 136752
 2011-08-03 00:43:35 +00:00
Nick Lewycky e8ae02dfb9 Teach InstCombine that lifetime intrincs aren't a real user on the result of a 
malloc call.

llvm-svn: 136732
 2011-08-02 22:08:01 +00:00
Nick Lewycky 99890a225f Lifetime intrinsics on undef are dead. 
llvm-svn: 136722
 2011-08-02 21:19:27 +00:00
Rafael Espindola c48e10cd54 Assume .cfi_startproc is the first thing in a function. If the function is 
externally visable, create a local symbol to use in the CFE. If not, use the
function label itself.

Fixes PR10420.

llvm-svn: 136716
 2011-08-02 20:24:22 +00:00
Bruno Cardoso Lopes 5ada908140 Make this kind of lowering to be supported by 256-bit instructions: 
shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
To:
  shuffle (vload ptr)), undef, <1, 1, 1, 1>
Fix PR10494

llvm-svn: 136691
 2011-08-02 16:06:18 +00:00
Benjamin Kramer c4189ff0fc Remove empty test. 
llvm-svn: 136675
 2011-08-02 02:47:45 +00:00
Owen Anderson bddf40e082 Revert r136503 and r136480 in an effort to fix non-determinism in the llvm-gcc buildbots on i386. Devang is looking into the root cause. 
llvm-svn: 136674
 2011-08-02 02:23:42 +00:00
Bruno Cardoso Lopes a8e3673816 Add v4f64 -> v2f32 fp_round support. Also add a testcase to exercise 
the legalizer. This commit together with the two previous ones fixes
PR10495.

llvm-svn: 136654
 2011-08-01 21:54:09 +00:00
Bruno Cardoso Lopes 7513939ddd Since vectors with all ones can't be created with a 256-bit instruction, 
avoid returning early for v8i32 types, which would only be valid for
vector with all zeros. Also split the handling of zeros and ones into separate
checking logic since they are handled differently. This fixes PR10547

llvm-svn: 136642
 2011-08-01 19:51:53 +00:00
Richard Osborne 0cc000ef29 Fix crash with varargs function with no named parameters. 
llvm-svn: 136623
 2011-08-01 16:45:59 +00:00
Rafael Espindola a3a44f3fc3 Add a small gep optimization I noticed was missing while reading some IL. 
llvm-svn: 136585
 2011-07-31 04:43:41 +00:00
Benjamin Kramer 99d53ff456 Remove InvalidateStructLayoutInfo from the ocaml bindings. 
llvm-svn: 136582
 2011-07-31 01:12:39 +00:00
Bill Wendling ad088e6724 Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338, 
r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444,
r136445, r136446, r136253 pending review.

llvm-svn: 136556
 2011-07-30 05:42:50 +00:00
Jakob Stoklund Olesen 5670f850c6 Revert "Don't check liveness of unallocatable registers." 
The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548
 2011-07-30 00:57:25 +00:00
Jakob Stoklund Olesen 95cc5440e9 Don't check liveness of unallocatable registers. 
This includes registers like EFLAGS and ST0-ST7. We don't check for
liveness issues in the verifier and scavenger because registers will
never be allocated from these classes.

While in SSA form, we do care about the liveness of unallocatable
unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for
MachineDCE and MachineSinking.

llvm-svn: 136541
 2011-07-29 23:36:21 +00:00
Eric Christopher aa5030066f Add support for the 'Q' constraint. 
Fixes rdar://9866494

llvm-svn: 136523
 2011-07-29 21:18:58 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support. 
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
 2011-07-29 20:26:09 +00:00
Devang Patel 3e02522fee Clean up debug info after reassociation. 
llvm-svn: 136480
 2011-07-29 19:00:35 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction. 
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
 2011-07-29 18:47:24 +00:00
Jim Grosbach 1c1d2438aa ARM update tests for CPS instruction. 
llvm-svn: 136472
 2011-07-29 17:39:27 +00:00
Bruno Cardoso Lopes 65ce5ea3ba Fix two tests that I crashed in the previous commits. The mask elts 
on the second half must be reindexed.

llvm-svn: 136454
 2011-07-29 02:05:28 +00:00
Bruno Cardoso Lopes 81eb193f2e Match VPERMIL masks more strictly and update the target specific mask 
generation to always catch the weird cases.

llvm-svn: 136453
 2011-07-29 01:31:15 +00:00
Bruno Cardoso Lopes d23709b18c Add v8i32 and v4i64 vpermil patterns 
llvm-svn: 136451
 2011-07-29 01:31:07 +00:00
Jakob Stoklund Olesen b28ee4115d Transfer implicit operands in NEONMoveFixPass. 
Later passes /are/ using this information when running the register
scavenger.

This fixes the second problem in PR10520.

llvm-svn: 136440
 2011-07-29 00:27:35 +00:00
Jakob Stoklund Olesen 9c3badceba Add -verify-arm-pseudo-expand. 
This hidden llc option runs the machine code verifier after expanding
ARM pseudo-instructions, but before if-conversion.

The machine code verifier is much better at pointing out liveness errors
that can trip up the register scavenger.

llvm-svn: 136439
 2011-07-29 00:27:32 +00:00
Eli Friedman 530341d748 Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they are combined together. <rdar://problem/9859829> 
llvm-svn: 136435
 2011-07-29 00:18:19 +00:00
Jim Grosbach b9bebc1b03 CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them. 
llvm-svn: 136408
 2011-07-28 21:59:38 +00:00
Jim Grosbach a03ab0e3dc ARM assembly parsing and encoding for BLX (immediate). 
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.

llvm-svn: 136406
 2011-07-28 21:57:55 +00:00
Jakob Stoklund Olesen b16081ce8c Handle REG_SEQUENCE with implicitly defined operands. 
Code like that would only be produced by bugpoint, but we should still
handle it correctly.

When a register is defined by a REG_SEQUENCE of undefs, the register
itself is undef. Previously, we would create a register with uses but no
defs.

Fixes part of PR10520.

llvm-svn: 136401
 2011-07-28 21:38:51 +00:00
Jim Grosbach 7f45559e86 Remove obsolete FIXME reference in comment. 
llvm-svn: 136400
 2011-07-28 21:37:05 +00:00
Jim Grosbach 864b609491 ARM assembly parsing and encoding for BFC and BFI. 
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).

llvm-svn: 136399
 2011-07-28 21:34:26 +00:00
Jim Grosbach 8b3184e540 ARM parsing and encoding for ADR. 
The label does not have a '#' prefix. Add parsing and encoding tests.

llvm-svn: 136360
 2011-07-28 16:33:54 +00:00
Jim Grosbach 4356636fc0 Update ARM tests for parsing and encoding of WFE, WFI and YIELD. 
llvm-svn: 136358
 2011-07-28 16:00:41 +00:00
Duncan Sands 483354758f Due to changes coming from the new LLVM type system, you now get 
bitcasts in this test rather than getelementptr instructions;
llvm-gcc produces two bitcasts, clang produces one.

llvm-svn: 136349
 2011-07-28 12:21:47 +00:00
Bruno Cardoso Lopes 76bc28bac6 Add patterns to generate copies for extract_subvector instead of 
using vextractf128. This will reduce the number of issued instruction
for several avx codes.

llvm-svn: 136323
 2011-07-28 01:26:50 +00:00
Bruno Cardoso Lopes eca99c4b5a Add a few patterns to match allzeros without having to use the fp unit. 
Take advantage that the 128-bit vpxor zeros the higher part and use it.
This also fixes PR10491

llvm-svn: 136321
 2011-07-28 01:26:43 +00:00
Bruno Cardoso Lopes 9e2a301216 Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also move 
a convert pattern close to the instruction definition.

llvm-svn: 136320
 2011-07-28 01:26:39 +00:00
Jim Grosbach 4059137f56 ARM parsing and encoding tests. 
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.

llvm-svn: 136312
 2011-07-28 00:37:03 +00:00
Evan Cheng eda1d4f3ba Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. 
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.

rdar://8204588

llvm-svn: 136292
 2011-07-27 23:22:03 +00:00
Jim Grosbach e37f7dc349 ARM assembly parsing and encoding for USUB16 and USUB8. 
llvm-svn: 136289
 2011-07-27 23:10:05 +00:00
Jim Grosbach 05f80d3add ARM assembly parsing and encoding for USAX. 
llvm-svn: 136288
 2011-07-27 23:07:00 +00:00
Kevin Enderby 5ef6c453a6 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates. 
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
 2011-07-27 23:01:50 +00:00
Jim Grosbach 16dd4adcbe Clean up tabs. 
llvm-svn: 136286
 2011-07-27 22:35:06 +00:00
Jim Grosbach 57e2d3cb84 ARM assembly parsing and encoding support for USAT and USAT16. 
Use range checked immediate operands for instructions. Add tests.

llvm-svn: 136285
 2011-07-27 22:34:17 +00:00
Jim Grosbach fea7a44a9b ARM assembly parsing and encoding tests for USAD8 and USADA8. 
llvm-svn: 136284
 2011-07-27 22:23:02 +00:00
Jim Grosbach 1644409b47 ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8. 
llvm-svn: 136282
 2011-07-27 22:13:08 +00:00
Jim Grosbach 1a3ddffc1c Fix comment copy/paste-o. 
llvm-svn: 136281
 2011-07-27 22:11:41 +00:00
Jim Grosbach 84ecab228a ARM assembly parsing and encoding tests for UQASX and UQSAX. 
llvm-svn: 136280
 2011-07-27 22:09:30 +00:00
Jim Grosbach 928f4175c0 ARM assembly parsing and encoding tests for UQADD16 and UQADD8. 
llvm-svn: 136279
 2011-07-27 22:08:14 +00:00
Jim Grosbach 39b062bfaa ARM assembly parsing and encoding for UMULL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136277
 2011-07-27 22:01:42 +00:00
Jim Grosbach 0c398b9c7e ARM assembly parsing and encoding for UMLAL. 
Fix parsing of the 's' suffix for the mnemonic. Add tests.

llvm-svn: 136274
 2011-07-27 21:58:11 +00:00
Jim Grosbach 121c21aba9 ARM assembly parsing and encoding tests for UMAAL. 
llvm-svn: 136272
 2011-07-27 21:53:42 +00:00
Jim Grosbach 7cfd32a006 ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8. 
llvm-svn: 136267
 2011-07-27 21:21:59 +00:00
Jim Grosbach 3f45383ef5 ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX. 
llvm-svn: 136266
 2011-07-27 21:20:45 +00:00