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14288 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes 46b9cde019 Add a AVX version of a simple i64 -> f64 bitcast. This could be 
triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.

llvm-svn: 139320
 2011-09-08 21:52:33 +00:00
Bruno Cardoso Lopes 51920a6191 Reapply testcase from r139309! 
llvm-svn: 139318
 2011-09-08 21:05:43 +00:00
Kevin Enderby 7b46bb8e32 Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom 
without a base symbol that must not have a relocation entry.

llvm-svn: 139316
 2011-09-08 20:53:44 +00:00
Bruno Cardoso Lopes f483c081b6 Remove this crashing test, until I figure out what's going wrong here 
llvm-svn: 139309
 2011-09-08 18:32:36 +00:00
Bruno Cardoso Lopes fb113a0051 Add AVX versions of blend vector operations and fix some issues noticed 
in Nadav's r139285 and r139287 commits.

1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions

llvm-svn: 139305
 2011-09-08 18:05:08 +00:00
Bruno Cardoso Lopes ea8d803bb0 Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl. 
Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.

llvm-svn: 139304
 2011-09-08 18:05:02 +00:00
Jim Grosbach 69a4def038 Add tests for Thumb2 LDRB indexed addressing w/ writeback. 
llvm-svn: 139292
 2011-09-08 16:49:36 +00:00
Nadav Rotem e114ba4465 This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll 
llvm-svn: 139288
 2011-09-08 08:43:23 +00:00
Nadav Rotem 354b7585de add a testcase for the previous patch 
llvm-svn: 139287
 2011-09-08 08:31:31 +00:00
Nadav Rotem 2550ba2a27 Add X86-SSE4 codegen support for vector-select. 
llvm-svn: 139285
 2011-09-08 08:11:19 +00:00
Eli Friedman 3d1b307672 Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881. 
llvm-svn: 139276
 2011-09-08 02:23:31 +00:00
Jim Grosbach 3343da5424 Thumb2 assembly parsing and encoding for LDR post-indexed. 
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.

llvm-svn: 139272
 2011-09-08 01:01:32 +00:00
Jim Grosbach c086f689f8 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Jim Grosbach 2392c53e73 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach f40ca22cd3 Thumb2 assembly parsing and encoding for LDRB(register). 
llvm-svn: 139266
 2011-09-07 23:17:00 +00:00
Jim Grosbach e0ebc1c396 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Jim Grosbach c8e3656b43 Thumb2 assembly parsing and encoding for LDRB(immediate). 
llvm-svn: 139258
 2011-09-07 21:41:25 +00:00
Jim Grosbach e2d68844bc Thumb2 assembly parsing and encoding for LDR(literal). 
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.

llvm-svn: 139257
 2011-09-07 21:33:16 +00:00
Owen Anderson 18d17aa6b7 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
Jim Grosbach fed3ab5bc1 Add tests for Thumb2 LDR(immediate) from r139254. 
llvm-svn: 139255
 2011-09-07 21:06:46 +00:00
Jim Grosbach 1c7406767e Thumb2 parsing and encoding for LDMDB. 
llvm-svn: 139251
 2011-09-07 19:57:53 +00:00
James Molloy 8067df9503 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Eli Friedman 02f2f89a98 Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()). 
This isn't exactly ideal, but it is good enough for the moment.

llvm-svn: 139245
 2011-09-07 18:48:32 +00:00
Jim Grosbach 5d5f4862eb Update test for 139243 
llvm-svn: 139244
 2011-09-07 18:40:06 +00:00
Jim Grosbach a31f223af8 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Owen Anderson cd5612d3a5 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
llvm-svn: 139240
 2011-09-07 17:55:19 +00:00
Duncan Sands 524c33a27f When inlining exception handling code into another function, ensure that 
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.

llvm-svn: 139236
 2011-09-07 16:44:14 +00:00
Duncan Sands 1257042b70 Another forgotten trampoline testcase. 
llvm-svn: 139230
 2011-09-07 10:05:14 +00:00
Duncan Sands d7430cea10 Forgot to add this trampoline testcase. 
llvm-svn: 139229
 2011-09-07 09:21:38 +00:00
Eli Friedman e978d2f644 Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM. 
(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)

llvm-svn: 139221
 2011-09-07 02:23:42 +00:00
Devang Patel 9de7a7db26 While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor. 
llvm-svn: 139208
 2011-09-07 00:07:58 +00:00
Owen Anderson 653cb03191 Teach BasicAA about the aliasing properties of memset_pattern16. 
Fixes PR10872 and <rdar://problem/10065079>.

llvm-svn: 139204
 2011-09-06 23:33:25 +00:00
Jim Grosbach 83a6188f18 Thumb2 parsing and encoding for ISB. 
llvm-svn: 139200
 2011-09-06 22:53:27 +00:00
Jim Grosbach 958feffa11 Thumb2 parsing and encoding for EOR. 
llvm-svn: 139199
 2011-09-06 22:44:50 +00:00
Jim Grosbach ed9399995a Thumb2 parsing and encoding for DSB. 
llvm-svn: 139194
 2011-09-06 22:19:40 +00:00
Jim Grosbach e95f46384e Thumb2 parsing and encoding for DMB. 
llvm-svn: 139193
 2011-09-06 22:14:58 +00:00
Nick Lewycky 474c455060 Disable these tests harder. They're XFAIL'd, but that means they still run, and 
these tests all infinitely recurse, bringing my system down into swapping hell.

llvm-svn: 139192
 2011-09-06 22:08:18 +00:00
Jim Grosbach c048b905b4 Thumb2 parsing and encoding for DBG. 
llvm-svn: 139191
 2011-09-06 22:06:40 +00:00
Jim Grosbach 565e2f5752 Thumb2 parsing and encoding for CMN and CMP. 
llvm-svn: 139188
 2011-09-06 21:44:58 +00:00
Nick Lewycky e0aa54bb98 This transform only handles two-operand AddRec's. Prevent it from trying to 
handle anything more complex. Fixes PR10383 again!

llvm-svn: 139186
 2011-09-06 21:42:18 +00:00
Jim Grosbach 70532e289f Thumb2 parsing and encoding for CLZ. 
llvm-svn: 139177
 2011-09-06 20:44:17 +00:00
Jim Grosbach 803898f119 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Owen Anderson b041e866b0 Port more encoding tests over to Thumb2 decoding tests. 
llvm-svn: 139171
 2011-09-06 20:26:34 +00:00
Jim Grosbach 6952281037 Thumb2 parsing and encoding for CDP/CDP2. 
llvm-svn: 139168
 2011-09-06 20:12:23 +00:00
Evan Cheng 0b758ed6ba Fix fall outs from my recent change on how carry bit is modeled during isel. 
Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745

llvm-svn: 139157
 2011-09-06 18:52:20 +00:00
Owen Anderson 58704ee442 Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's. 
llvm-svn: 139150
 2011-09-06 18:14:09 +00:00
Jakob Stoklund Olesen 50ef7611aa Atomic pseudos don't use (as in read) CPSR. They clobber it. 
llvm-svn: 139148
 2011-09-06 17:40:35 +00:00
Duncan Sands a098436b32 Split the init.trampoline intrinsic, which currently combines GCC's 
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC.  While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function.  To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function.  Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!).  Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC.  Patch mostly by Sanjoy Das.

llvm-svn: 139140
 2011-09-06 13:37:06 +00:00
Nick Lewycky 658bdb5133 The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was 
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!

llvm-svn: 139133
 2011-09-06 05:05:14 +00:00
Nick Lewycky b1438c763a Revert r139126 due to selfhost failures reported by buildbots. 
llvm-svn: 139130
 2011-09-06 02:43:13 +00:00
Nick Lewycky c4c43fbb07 Teach SCEV to report a max backedge count in one interesting case in 
HowFarToZero; the case for a canonical loop.

llvm-svn: 139126
 2011-09-05 23:25:16 +00:00
Benjamin Kramer 4b79c21ef2 InstSimplify: Don't try to replace an extractvalue/insertvalue pair with the original value if types don't match. 
Fixes clang selfhost.

llvm-svn: 139120
 2011-09-05 18:16:19 +00:00
Duncan Sands 29192d042e Delete trivial landing pads that just continue unwinding the caught 
exception.

llvm-svn: 139117
 2011-09-05 12:57:57 +00:00
Duncan Sands fd26a954a8 Add some simple insertvalue simplifications, for the purpose of cleaning 
up do-nothing exception handling code produced by dragonegg.

llvm-svn: 139113
 2011-09-05 06:52:48 +00:00
Dan Gohman 5423017526 Revert r129875, XFAILing this test for arm, since the fix was reverted. 
llvm-svn: 139058
 2011-09-03 00:14:24 +00:00
Jakob Stoklund Olesen 1f72dd40c7 Pseudo CMOV instructions don't clobber EFLAGS. 
The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

llvm-svn: 139057
 2011-09-02 23:52:55 +00:00
Jim Grosbach f347d1d772 Thumb2 parsing and encoding for CBZ/CBNZ. 
llvm-svn: 139054
 2011-09-02 23:46:10 +00:00
Jim Grosbach 34842ceb97 Thumb2 parsing and encoding for BXJ. 
llvm-svn: 139053
 2011-09-02 23:43:09 +00:00
Jim Grosbach 9e55023ca7 Thumb2 parsing and encoding for BIC. 
llvm-svn: 139052
 2011-09-02 23:37:54 +00:00
Jim Grosbach 93e3fd29b2 Thumb2 parsing and encoding for BFI. 
llvm-svn: 139051
 2011-09-02 23:28:46 +00:00
Jim Grosbach be31448d99 Thumb2 parsing and encoding for BFC. 
llvm-svn: 139050
 2011-09-02 23:25:46 +00:00
Jim Grosbach a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Bill Wendling 4aa2573748 Try to eliminate the use of the 'unwind' instruction. 
llvm-svn: 139046
 2011-09-02 22:41:11 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Jim Grosbach a216debb37 Thumb2 parsing and encoding for ASR. 
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.

llvm-svn: 139040
 2011-09-02 21:28:54 +00:00
Bill Wendling 912668d998 Better fix for this testcase. Update it to the new EH scheme entirely. 
llvm-svn: 139039
 2011-09-02 21:27:08 +00:00
Bill Wendling 17706bcffb Update for new EH stuff. (I'm not sure if this is 100% correct.) 
llvm-svn: 139038
 2011-09-02 21:24:17 +00:00
Andrew Trick 310a448cfe Test case update for unroll-scev. 
llvm-svn: 139037
 2011-09-02 21:21:03 +00:00
Kevin Enderby 5b03f72292 Change X86 disassembly to print immediates values as signed by default. Special 
case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028
 2011-09-02 20:01:23 +00:00
Jim Grosbach 370e923434 Thumb2 parsing and encoding for AND (register). 
llvm-svn: 139021
 2011-09-02 18:41:35 +00:00
Jim Grosbach 2761155203 Thumb2 parsing and encoding for ADD (register). 
llvm-svn: 139017
 2011-09-02 18:14:46 +00:00
Duncan Sands 5c04c62765 Darwin wants ctors/dtors to be ordered the other way round to linux. 
llvm-svn: 139015
 2011-09-02 18:07:19 +00:00
Kevin Enderby 54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
llvm-svn: 139014
 2011-09-02 18:03:03 +00:00
Jim Grosbach b861b2b475 Tests for Thumb2 AND (immediate) instruction. 
llvm-svn: 139013
 2011-09-02 17:44:27 +00:00
Jakub Staszak 63a3a0e010 Extra CHECK-NOT to make sure that GVN transform works properly. 
llvm-svn: 139012
 2011-09-02 17:40:39 +00:00
Andrew Trick 4a31ba3bae -unroll-scev flag removal 
llvm-svn: 139010
 2011-09-02 17:36:14 +00:00
Jim Grosbach c302f5cce7 Add FIXME. Thumb2 ADR encoding choice is non-trivial. 
llvm-svn: 139008
 2011-09-02 17:21:59 +00:00
Jakub Staszak 057d423e4b ConstantVector returns arbitrary value for the wrong index. 
This fixes PR10813.

llvm-svn: 139006
 2011-09-02 15:43:43 +00:00
Jakub Staszak 7470fb01d0 Compare type size instead of type _store_ size to make sure that BitCastInst 
will be valid. This fixes PR10820.

llvm-svn: 139005
 2011-09-02 14:57:37 +00:00
Kalle Raiskila f5769c1070 Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction. 
llvm-svn: 139004
 2011-09-02 10:05:01 +00:00
Craig Topper 94ce535647 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. 
llvm-svn: 138997
 2011-09-02 04:17:54 +00:00
Bill Wendling 723cec7a5f Update to new EH scheme. 
llvm-svn: 138989
 2011-09-02 01:25:11 +00:00
Dan Gohman 3767be9aee Revert r131152, r129796, r129761. This code is currently considered 
to be unreliable on platforms which require memcpy calls, and it is
complicating broader legalize cleanups. It is hoped that these cleanups
will make memcpy byval easier to implement in the future.

llvm-svn: 138977
 2011-09-01 23:07:08 +00:00
Benjamin Kramer 6397051ece Don't drop alignment info on local common symbols. 
- On COFF the .lcomm directive has an alignment argument.
- On ELF we fall back to .local + .comm

Based on a patch by NAKAMURA Takumi.

Fixes PR9337, PR9483 and PR10128.

llvm-svn: 138976
 2011-09-01 23:04:27 +00:00
Eli Friedman 4028a51c74 Fix test; sorry for any inconvenience. 
llvm-svn: 138966
 2011-09-01 21:25:42 +00:00
Eli Friedman 71f5c2f158 Fix an issue with the IR sink pass found by inspection. (I'm not sure anyone is actually using this, but might as well fix it since I found the issue.) 
llvm-svn: 138965
 2011-09-01 21:21:24 +00:00
Eli Friedman cc6e92892f Add missing newline. 
llvm-svn: 138964
 2011-09-01 21:20:11 +00:00
Benjamin Kramer c032617581 XFAIL this test on arm until the backend is fixed. 
llvm-svn: 138955
 2011-09-01 18:40:03 +00:00
Benjamin Kramer 0f6ff8cb2b This test depends on cmov being available. 
llvm-svn: 138954
 2011-09-01 18:40:01 +00:00
Jakob Stoklund Olesen 5dc87d0f4d Permit remat of partial register defs when it is safe. 
An instruction may define part of a register where the other bits are
undefined. In that case, it is safe to rematerialize the instruction.
For example:

  %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def>

The extra <imp-def> operand indicates that the instruction does not read
the other parts of the virtual register, so a remat is safe.

This patch simply allows multiple def operands for the virtual register.
It is MI->readsVirtualRegister() that determines if we depend on a
previous value so remat is impossible.

llvm-svn: 138953
 2011-09-01 18:27:51 +00:00
Jim Grosbach f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Bruno Cardoso Lopes f61d1c072e Fix vbroadcast matching logic to early unmatch if the node doesn't have 
only one use. Fix PR10825.

llvm-svn: 138951
 2011-09-01 18:15:06 +00:00
Owen Anderson 35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jakob Stoklund Olesen 6357fa2f06 Prevent remat of partial register redefinitions. 
An instruction that redefines only part of a larger register can never
be rematerialized since the virtual register value depends on the old
value in other parts of the register.

This was fixed for the inline spiller in r138794.  This patch fixes the
problem for all register allocators, and includes a small test case.

<rdar://problem/10032939>

llvm-svn: 138944
 2011-09-01 17:18:50 +00:00
Bill Wendling 185d377597 Update to new EH scheme. 
llvm-svn: 138933
 2011-09-01 01:28:25 +00:00
Bill Wendling d33e3007fa Update to new EH scheme. 
llvm-svn: 138928
 2011-09-01 01:08:21 +00:00
Bill Wendling 3b17c1b48d Update to new EH scheme. 
llvm-svn: 138927
 2011-09-01 01:02:41 +00:00
Bill Wendling e88632d667 Update some tests to the new EH scheme. 
llvm-svn: 138925
 2011-09-01 00:58:03 +00:00
Andrew Trick 832a6a1909 PreRA scheduler should avoid cloning compares. 
Added canClobberReachingPhysRegUse() to handle a particular pattern in
which a two-address instruction could be forced to interfere with
EFLAGS, causing a compare to be unnecessarilly cloned.
Fixes rdar://problem/5875261

llvm-svn: 138924
 2011-09-01 00:54:31 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Bill Wendling 080f40a49d Reenable test. 
llvm-svn: 138916
 2011-08-31 23:08:05 +00:00
Bill Wendling 54b91028f0 Revert accidental commit 
llvm-svn: 138915
 2011-08-31 23:07:46 +00:00
Eli Friedman c472975fd9 Disable this test until Bill fixes it properly. 
llvm-svn: 138914
 2011-08-31 23:03:30 +00:00
Bill Wendling 5624fe0cff Update to new EH scheme. 
llvm-svn: 138908
 2011-08-31 21:50:07 +00:00
Bill Wendling e336599f6d Update to new EH scheme. 
llvm-svn: 138906
 2011-08-31 21:44:24 +00:00
Bill Wendling 55fb73a6e0 Remove old declare statements. 
llvm-svn: 138905
 2011-08-31 21:41:20 +00:00
Bill Wendling 22055c713f Update more tests to the new EH scheme. 
llvm-svn: 138904
 2011-08-31 21:40:15 +00:00
Bill Wendling d4e871404d Update more tests to the new EH scheme. 
llvm-svn: 138903
 2011-08-31 21:39:05 +00:00
Eli Friedman 293c31b81c Add tests for the transformations SCCP can do on atomic loads and stores (which are safe without any modifications). 
llvm-svn: 138902
 2011-08-31 21:37:06 +00:00
Bill Wendling c4c24f03e9 Revert r138894. This was failing on cmake-clang-i686-msvc10. 
llvm-svn: 138900
 2011-08-31 21:20:25 +00:00
Bill Wendling e6174a2c85 Update more tests to the new EH scheme. 
llvm-svn: 138894
 2011-08-31 21:04:11 +00:00
Bill Wendling b1e680fd3f Update the tests to the new EH scheme. 
llvm-svn: 138891
 2011-08-31 20:55:40 +00:00
Owen Anderson a455a0b1e7 Fix encoding for tBcc with immediate offset operand. 
llvm-svn: 138889
 2011-08-31 20:26:14 +00:00
Jim Grosbach 6a69d6902f Run the Thumb1 parser tests in Thumb2 mode, as well. 
Thumb2 is a superset of Thumb1, so all of the encodings should still work.

llvm-svn: 138883
 2011-08-31 19:50:28 +00:00
Jim Grosbach 6eb213c919 Thumb NOP encoding varies depending on ARCH revision. 
llvm-svn: 138876
 2011-08-31 18:35:46 +00:00
Owen Anderson 5c160fd243 Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels. 
llvm-svn: 138874
 2011-08-31 18:30:20 +00:00
Eli Friedman 7c3bdede25 Generic expansion for atomic load/store into cmpxchg/atomicrmw xchg; implements 64-bit atomic load/store for ARM. 
llvm-svn: 138872
 2011-08-31 18:26:09 +00:00
Jim Grosbach af8c3cc710 Thumb2 parsing and encoding for ADC(register). 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

llvm-svn: 138871
 2011-08-31 18:23:08 +00:00
Eli Friedman 1ccecbb9d3 64-bit atomic cmpxchg for ARM. 
llvm-svn: 138868
 2011-08-31 17:52:22 +00:00
David Greene cdef71f4f3 Compress Repeated Byte Output 
Emit a repeated sequence of bytes using .zero.  This saves an enormous
amount of asm file space for certain programs.

llvm-svn: 138864
 2011-08-31 17:30:56 +00:00
Jim Grosbach 6d606fbe14 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Benjamin Kramer 5247ca0ae5 This test requires sse, otherwise x87 ops will block tailcall optimization 
llvm-svn: 138859
 2011-08-31 16:49:05 +00:00
Bruno Cardoso Lopes 9fc6b8be03 - Move all MOVSS and MOVSD patterns close to their definitions 
- Duplicate some store patterns to their AVX forms!
- Catched a bug while restricting the patterns subtarget, fix it
  and update a testcase to check it properly

llvm-svn: 138851
 2011-08-31 03:04:20 +00:00
Evan Cheng cb1e5bae4c Fix (movhps load) lowering / pattern to match more cases. rdar://10050549 
llvm-svn: 138848
 2011-08-31 02:05:24 +00:00
Eli Friedman 2c7bb52f56 Some minor cleanups for r138845. 
llvm-svn: 138846
 2011-08-31 00:41:05 +00:00
Eli Friedman c3f9c4a852 Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. 
llvm-svn: 138845
 2011-08-31 00:31:29 +00:00
Benjamin Kramer 50cabb5de4 Fix test typo. 
llvm-svn: 138843
 2011-08-31 00:02:59 +00:00
Rafael Espindola a45c20b049 Remove the old tail duplication pass. It is not used and is unable to update 
ssa, so it has to be run really early in the pipeline. Any replacement
should probably use the SSAUpdater.

llvm-svn: 138841
 2011-08-30 23:03:45 +00:00
Owen Anderson 2fa06a7226 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00
Owen Anderson fdf3cd7f2b Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels. 
llvm-svn: 138837
 2011-08-30 22:15:17 +00:00
Owen Anderson d16fb43b1f Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels. 
llvm-svn: 138835
 2011-08-30 22:10:03 +00:00
Owen Anderson 543c89fb15 Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping. 
llvm-svn: 138834
 2011-08-30 22:03:20 +00:00
Rafael Espindola 1450f61e8f Add a triple. 
llvm-svn: 138831
 2011-08-30 21:19:37 +00:00
Owen Anderson b359367a3d Remove empty file. 
llvm-svn: 138830
 2011-08-30 21:17:20 +00:00
Owen Anderson e316e5b2ad Speculatively revert r138809 in an attempt to fix DragonEgg. 
llvm-svn: 138829
 2011-08-30 21:11:06 +00:00
Owen Anderson 2e282257ed Port Thumb2 assembler tests over to disassembler tests. 
llvm-svn: 138822
 2011-08-30 20:03:11 +00:00
Rafael Espindola 9f2edc8d2c Some test code to check if correct code is being generated. 
Patch by Sanjoy Das.

llvm-svn: 138820
 2011-08-30 19:51:29 +00:00
Owen Anderson d708ec4c6a When walking backwards to eliminate final stores to allocas at the end of a function, encountering an unrelated store should not cause us to give up like encountering a load does. 
llvm-svn: 138809
 2011-08-30 18:51:55 +00:00
Andrew Trick d74c19449e Lit option for ignoring stderr output. 
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!

llvm-svn: 138804
 2011-08-30 17:42:33 +00:00
Roman Divacky 71038e7021 Set CR1EQ only when lowering vararg floating arguments (not any vararg 
arguments as before), unset CR1EQ otherwise.

llvm-svn: 138802
 2011-08-30 17:04:16 +00:00
Craig Topper 4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
llvm-svn: 138795
 2011-08-30 07:09:35 +00:00
Evan Cheng e891654a58 Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical 
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791
 2011-08-30 01:34:54 +00:00
Owen Anderson 3e0aa03fe9 Add missing encoding information for some of the GPR<->FP register moves. 
llvm-svn: 138780
 2011-08-29 23:15:25 +00:00
Jim Grosbach 4b23a65582 Remove redundant tests from XFAIL'ed test file. 
llvm-svn: 138779
 2011-08-29 23:04:04 +00:00
Jim Grosbach 55d6f43cab Thumb2 assembly parsing and encoding support for ADC(immediate). 
llvm-svn: 138778
 2011-08-29 23:01:38 +00:00
Jim Grosbach 89a12be8bb Remove test file. Superceded by other more exhaustive tests. 
llvm-svn: 138777
 2011-08-29 23:00:19 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Kevin Enderby 7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
llvm-svn: 138771
 2011-08-29 22:06:28 +00:00
Eli Friedman 850b9a9a84 Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. 
llvm-svn: 138768
 2011-08-29 21:15:46 +00:00
Bill Wendling e79ce47ad7 Update tests to new EH model. Add landingpad instructions to landing pads. 
llvm-svn: 138759
 2011-08-29 20:39:23 +00:00