3de5b8e4c1
[indvars] Fix bugs in floating point IV range checks noticed by inspection.
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llvm-svn: 139574
2011-09-13 01:59:32 +00:00
54a109845d
Conditionalize indvars test that relies on SCEV expansion of geps,
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which is only relevant with canonical IVs
llvm-svn: 139556
2011-09-12 23:13:57 +00:00
bf6e1e2717
Change testcase commandline to be more strict and silence buildbots
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llvm-svn: 139554
2011-09-12 22:59:26 +00:00
ff8d8a830e
Fix PR10845. SUBREG_TO_REG shouldn't be used when the input and
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destination types are equal!
llvm-svn: 139553
2011-09-12 22:59:23 +00:00
a8315c3f2b
indvars test only relevant for -enable-iv-rewrite.
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Otherwise this case is now covered by no-iv-rewrite.ll.
llvm-svn: 139552
2011-09-12 22:59:00 +00:00
1b7090c9b3
Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally clear to me what this test is doing. Could someone on an ELF platform check?
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llvm-svn: 139549
2011-09-12 22:40:31 +00:00
2a206c44b7
Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either.
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llvm-svn: 139542
2011-09-12 21:28:46 +00:00
973d2921e8
Revert the wrong part of r139528, and fix testcases.
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llvm-svn: 139541
2011-09-12 21:24:07 +00:00
4a9eb5f8dc
Fix encoding of PC-relative LDRSHW with an immediate offset.
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llvm-svn: 139537
2011-09-12 20:36:51 +00:00
d2e61e1f70
Conditionalize indvars tests that rely on SCEV expansion of geps,
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which is relevant with canonical IVs. Anything else being checked by
these tests is already covered by early CSE.
llvm-svn: 139535
2011-09-12 20:26:34 +00:00
be7a086f58
Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.
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However with this fix it does now.
Basically the operand order for the x86 target specific node
is not the same as the instruction, but since the intrinsic need that
specific order at the instruction definition, just change the order
during legalization. Also, there were some wrong invertions of condition
codes, such as GE => LE, GT => LT, fix that too. Fix PR10907.
llvm-svn: 139528
2011-09-12 19:30:40 +00:00
a9ebf6fb64
Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.
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llvm-svn: 139522
2011-09-12 18:56:30 +00:00
30e8db98b8
Removing indvars tests that directly test canonical IVs and nothing else.
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llvm-svn: 139518
2011-09-12 18:33:08 +00:00
183013d8d4
Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for default change.
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llvm-svn: 139517
2011-09-12 18:28:44 +00:00
57ca95961b
Fix mistake in test runline.
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llvm-svn: 139505
2011-09-12 17:32:58 +00:00
8c6fb3af6e
Test case for r139453, WidenIV::GetExtendedOperandRecurrence.
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llvm-svn: 139504
2011-09-12 17:20:57 +00:00
97a2a5c4dc
Associate a MemOperand with LDWCP nodes introduced during ISel.
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This information is required if we want LDWCP to be hoisted out of loops.
llvm-svn: 139495
2011-09-12 14:43:23 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
501f541b45
Really un-XFAIL the testcase, like I said I would in r139458.
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llvm-svn: 139459
2011-09-10 02:02:27 +00:00
d9917bef6c
Fixed an assert from:
...
assert("not implemented for target shuffle node");
to:
assert(0 && "not implemented for target shuffle node");
This causes a test failure in CodeGen/X86/palignr.ll which has
been marked as XFAIL for the time being.
Test failure filed at PR10901.
llvm-svn: 139454
2011-09-10 01:26:21 +00:00
b908b7af31
Thumb2 parsing and encoding for MOV(immediate).
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Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
llvm-svn: 139440
2011-09-10 00:15:36 +00:00
5624707684
Fix test cases.
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Generate code for Mips32r1 unless a Mips32r2 feature is tested.
llvm-svn: 139433
2011-09-09 23:14:58 +00:00
53db43b560
LDM writeback is not allowed if Rn is in the target register list.
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llvm-svn: 139432
2011-09-09 23:13:33 +00:00
5bfb0e0a85
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
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llvm-svn: 139422
2011-09-09 22:24:36 +00:00
29cfe6c368
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
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llvm-svn: 139415
2011-09-09 21:48:23 +00:00
b7910b79f5
Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897.
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llvm-svn: 139407
2011-09-09 21:04:06 +00:00
4444daeec5
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
de838daefd
Implement vector-select support for avx256. Refactor the vblend implementation to have tablegen match the instruction by the node type
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llvm-svn: 139400
2011-09-09 20:29:17 +00:00
62c33955e2
Thumb2 assembly parsing and encoding for MLA and MLS.
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llvm-svn: 139399
2011-09-09 20:24:45 +00:00
b4c32d92ea
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
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llvm-svn: 139397
2011-09-09 20:19:28 +00:00
54175d519e
Tidy up formatting a bit.
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llvm-svn: 139396
2011-09-09 20:17:49 +00:00
89b1775256
Thumb2 assembly parsing and encoding for LSL.
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llvm-svn: 139395
2011-09-09 20:05:38 +00:00
2119a62aae
Thumb2 assembly parsing and encoding for LDRT.
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llvm-svn: 139393
2011-09-09 20:02:15 +00:00
9b11580719
Thumb2 assembly parsing and encoding for LDRSHT.
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llvm-svn: 139392
2011-09-09 20:01:18 +00:00
d2165b829f
Thumb2 assembly parsing and encoding for LDRSH.
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llvm-svn: 139391
2011-09-09 19:54:30 +00:00
f1b71de4ea
Thumb2 assembly parsing and encoding for LDRSBT.
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llvm-svn: 139390
2011-09-09 19:49:06 +00:00
779a2bee7b
Thumb2 assembly parsing and encoding for LDRSB.
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llvm-svn: 139389
2011-09-09 19:42:40 +00:00
5af572426d
Thumb2 assembly parsing and encoding for LDRH.
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llvm-svn: 139386
2011-09-09 19:13:53 +00:00
732f90a61c
Shuffle a bit.
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llvm-svn: 139385
2011-09-09 19:09:54 +00:00
d22a1c6c95
Drop support for Allegrex. Allegrex implements a variant of Mips2.
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llvm-svn: 139383
2011-09-09 19:00:51 +00:00
a05627ebaf
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
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llvm-svn: 139381
2011-09-09 18:37:27 +00:00
a042ed5cae
Add FIXME.
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llvm-svn: 139371
2011-09-09 16:45:31 +00:00
ba60b04148
Mark the eh.typeid.for intrinsic as being 'const', which it is inside
...
any given function. As pointed out by John McCall, this is needed to
have redundant eh.typeid.for tests be eliminated in the presence of
cleanups.
llvm-svn: 139360
2011-09-09 07:50:37 +00:00
e812f9eed5
Add disassembler test for Intel syntax. Tests r139353.
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llvm-svn: 139356
2011-09-09 06:35:44 +00:00
df1df7edf1
Change default target architecture from Mips1 to Mips32r1 in preparation for
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removing support for Mips1 and Mips2.
This change and the ones that follow have been discussed with and approved by
Bruno.
llvm-svn: 139344
2011-09-09 01:13:27 +00:00
9d904e1a97
Directly point debug info to the stack slot of the arugment, instead of trying to keep track of vreg in which it the arugment is copied. The LiveDebugVariable can keep track of variable's ranges.
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llvm-svn: 139330
2011-09-08 22:59:09 +00:00
2fefa427d5
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
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llvm-svn: 139328
2011-09-08 22:42:49 +00:00
7db8d697cf
Thumb2 assembly parsing and encoding for LDRD(immediate).
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Refactor operand handling for STRD as well. Tests for that forthcoming.
llvm-svn: 139322
2011-09-08 22:07:06 +00:00
46b9cde019
Add a AVX version of a simple i64 -> f64 bitcast. This could be
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triggered using llc with -O0, which wouldn't let it be folded and
expose the lack of this pattern.
llvm-svn: 139320
2011-09-08 21:52:33 +00:00
51920a6191
Reapply testcase from r139309!
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llvm-svn: 139318
2011-09-08 21:05:43 +00:00
7b46bb8e32
Fix a Darwin x86_64 special case of a jmp to a temporary symbol from an atom
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without a base symbol that must not have a relocation entry.
llvm-svn: 139316
2011-09-08 20:53:44 +00:00
f483c081b6
Remove this crashing test, until I figure out what's going wrong here
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llvm-svn: 139309
2011-09-08 18:32:36 +00:00
fb113a0051
Add AVX versions of blend vector operations and fix some issues noticed
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in Nadav's r139285 and r139287 commits.
1) Rename vsel.ll to a more descriptive name
2) Change the order of BLEND operands to "Op1, Op2, Cond", this is
necessary because PBLENDVB is already used in different places with
this order, and it was being emitted in the wrong way for vselect
3) Add AVX patterns and tests for the same SSE41 instructions
llvm-svn: 139305
2011-09-08 18:05:08 +00:00
ea8d803bb0
Fix PR10844: Add patterns to cover non foldable versions of X86vzmovl.
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Triggered using llc -O0. Also fix some SET0PS patterns to their AVX
forms and test it on the testcase.
llvm-svn: 139304
2011-09-08 18:05:02 +00:00
69a4def038
Add tests for Thumb2 LDRB indexed addressing w/ writeback.
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llvm-svn: 139292
2011-09-08 16:49:36 +00:00
e114ba4465
This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll
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llvm-svn: 139288
2011-09-08 08:43:23 +00:00
354b7585de
add a testcase for the previous patch
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llvm-svn: 139287
2011-09-08 08:31:31 +00:00
2550ba2a27
Add X86-SSE4 codegen support for vector-select.
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llvm-svn: 139285
2011-09-08 08:11:19 +00:00
3d1b307672
Fix the logic in BasicAliasAnalysis::aliasGEP for comparing GEP's with variable differences so that it actually does something sane. Fixes PR10881.
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llvm-svn: 139276
2011-09-08 02:23:31 +00:00
3343da5424
Thumb2 assembly parsing and encoding for LDR post-indexed.
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More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
llvm-svn: 139272
2011-09-08 01:01:32 +00:00
c086f689f8
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
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Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
llvm-svn: 139270
2011-09-08 00:39:19 +00:00
2392c53e73
Thumb2 assembly parsing and encoding for LDRBT.
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llvm-svn: 139267
2011-09-07 23:39:14 +00:00
f40ca22cd3
Thumb2 assembly parsing and encoding for LDRB(register).
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llvm-svn: 139266
2011-09-07 23:17:00 +00:00
e0ebc1c396
Thumb2 assembly parsing and encoding for LDR(register).
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llvm-svn: 139264
2011-09-07 23:10:15 +00:00
c8e3656b43
Thumb2 assembly parsing and encoding for LDRB(immediate).
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llvm-svn: 139258
2011-09-07 21:41:25 +00:00
e2d68844bc
Thumb2 assembly parsing and encoding for LDR(literal).
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Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.
llvm-svn: 139257
2011-09-07 21:33:16 +00:00
18d17aa6b7
Create Thumb2 versions of STC/LDC, and reenable the relevant tests.
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llvm-svn: 139256
2011-09-07 21:10:42 +00:00
fed3ab5bc1
Add tests for Thumb2 LDR(immediate) from r139254.
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llvm-svn: 139255
2011-09-07 21:06:46 +00:00
1c7406767e
Thumb2 parsing and encoding for LDMDB.
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llvm-svn: 139251
2011-09-07 19:57:53 +00:00
8067df9503
Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.
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llvm-svn: 139250
2011-09-07 19:42:28 +00:00
02f2f89a98
Fix atomic load and store on x86 to pass -verify-machineinstrs (and possibly fix some subtle bugs involving passes which check mayStore()).
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This isn't exactly ideal, but it is good enough for the moment.
llvm-svn: 139245
2011-09-07 18:48:32 +00:00
5d5f4862eb
Update test for 139243
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llvm-svn: 139244
2011-09-07 18:40:06 +00:00
a31f223af8
Thumb2 parsing and encoding for LDMIA.
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Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
llvm-svn: 139242
2011-09-07 18:05:34 +00:00
cd5612d3a5
Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.
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llvm-svn: 139240
2011-09-07 17:55:19 +00:00
524c33a27f
When inlining exception handling code into another function, ensure that
...
duplicate tests are eliminated (for example if the two functions both have
a catch clause catching the same type, ensure the redundant one is removed).
Note that it would probably be safe to say that eh.typeid.for is 'const',
but since two calls to it with the same argument can give different results
(but only if the calls are in different functions), it seems more correct to
mark it only 'pure'; this doesn't get in the way of the optimization.
llvm-svn: 139236
2011-09-07 16:44:14 +00:00
1257042b70
Another forgotten trampoline testcase.
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llvm-svn: 139230
2011-09-07 10:05:14 +00:00
d7430cea10
Forgot to add this trampoline testcase.
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llvm-svn: 139229
2011-09-07 09:21:38 +00:00
e978d2f644
Relax the MemOperands on atomics a bit. Fixes -verify-machineinstrs failures for atomic laod/store on ARM.
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(The fix for the related failures on x86 is going to be nastier because we actually need Acquire memoperands attached to the atomic load instrs, etc.)
llvm-svn: 139221
2011-09-07 02:23:42 +00:00
9de7a7db26
While sinking machine instructions, sink matching DBG_VALUEs also otherwise live debug variable pass will drop DBG_VALUEs on the floor.
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llvm-svn: 139208
2011-09-07 00:07:58 +00:00
653cb03191
Teach BasicAA about the aliasing properties of memset_pattern16.
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Fixes PR10872 and <rdar://problem/10065079>.
llvm-svn: 139204
2011-09-06 23:33:25 +00:00
83a6188f18
Thumb2 parsing and encoding for ISB.
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llvm-svn: 139200
2011-09-06 22:53:27 +00:00
958feffa11
Thumb2 parsing and encoding for EOR.
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llvm-svn: 139199
2011-09-06 22:44:50 +00:00
ed9399995a
Thumb2 parsing and encoding for DSB.
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llvm-svn: 139194
2011-09-06 22:19:40 +00:00
e95f46384e
Thumb2 parsing and encoding for DMB.
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llvm-svn: 139193
2011-09-06 22:14:58 +00:00
474c455060
Disable these tests harder. They're XFAIL'd, but that means they still run, and
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these tests all infinitely recurse, bringing my system down into swapping hell.
llvm-svn: 139192
2011-09-06 22:08:18 +00:00
c048b905b4
Thumb2 parsing and encoding for DBG.
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llvm-svn: 139191
2011-09-06 22:06:40 +00:00
565e2f5752
Thumb2 parsing and encoding for CMN and CMP.
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llvm-svn: 139188
2011-09-06 21:44:58 +00:00
e0aa54bb98
This transform only handles two-operand AddRec's. Prevent it from trying to
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handle anything more complex. Fixes PR10383 again!
llvm-svn: 139186
2011-09-06 21:42:18 +00:00
70532e289f
Thumb2 parsing and encoding for CLZ.
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llvm-svn: 139177
2011-09-06 20:44:17 +00:00
803898f119
Thumb2 parsing and encoding for CLREX.
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llvm-svn: 139172
2011-09-06 20:27:04 +00:00
b041e866b0
Port more encoding tests over to Thumb2 decoding tests.
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llvm-svn: 139171
2011-09-06 20:26:34 +00:00
6952281037
Thumb2 parsing and encoding for CDP/CDP2.
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llvm-svn: 139168
2011-09-06 20:12:23 +00:00
0b758ed6ba
Fix fall outs from my recent change on how carry bit is modeled during isel.
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Now the 'S' instructions, e.g. ADDS, treat S bit as optional operand as well.
Also fix isel hook to correctly set the optional operand.
rdar://10073745
llvm-svn: 139157
2011-09-06 18:52:20 +00:00
58704ee442
Try again at r138809 (make DSE more aggressive in removing dead stores at the end of a function), now with less deleting stores before memcpy's.
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llvm-svn: 139150
2011-09-06 18:14:09 +00:00
50ef7611aa
Atomic pseudos don't use (as in read) CPSR. They clobber it.
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llvm-svn: 139148
2011-09-06 17:40:35 +00:00
a098436b32
Split the init.trampoline intrinsic, which currently combines GCC's
...
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
llvm-svn: 139140
2011-09-06 13:37:06 +00:00
658bdb5133
The logic inside getMulExpr to simplify {a,+,b}*{c,+,d} was wrong, which was
...
visible given a=b=c=d=1, on iteration #1 (the second iteration). Replace it with
correct math. Fixes PR10383!
llvm-svn: 139133
2011-09-06 05:05:14 +00:00
b1438c763a
Revert r139126 due to selfhost failures reported by buildbots.
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llvm-svn: 139130
2011-09-06 02:43:13 +00:00
Andrew Trick