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14288 Commits

Author SHA1 Message Date
Jim Grosbach 82dd698575 Thumb2 assembly parsing and encoding for RRX. 
llvm-svn: 139831
 2011-09-15 19:52:43 +00:00
Jim Grosbach 8082169d7c Thumb2 assembly parsing and encoding for ROR. 
llvm-svn: 139830
 2011-09-15 19:50:04 +00:00
Jim Grosbach 4cbe06e7f8 Thumb2 assembly parsing and encoding for REV16/REVSH. 
llvm-svn: 139828
 2011-09-15 19:46:13 +00:00
Jakob Stoklund Olesen 53e2e48de7 VirtRegMap is counting spill slots, not register spills. 
Fix the stats counters to reflect that.

llvm-svn: 139819
 2011-09-15 18:31:13 +00:00
Bruno Cardoso Lopes fa1ca3070b Change all checks regarding the presence of any SSE level to always 
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite

llvm-svn: 139817
 2011-09-15 18:27:36 +00:00
Jim Grosbach ab154f0b65 Thumb2 assembly parsing and encoding for REV. 
llvm-svn: 139813
 2011-09-15 18:13:30 +00:00
Jim Grosbach 5c5c42bf76 Thumb2 assembly parsing and encoding for RBIT. 
llvm-svn: 139811
 2011-09-15 18:07:14 +00:00
Jim Grosbach 5e18a31da4 Thumb2 assembly parsing and encoding for signed saturating arithmetic insns. 
llvm-svn: 139810
 2011-09-15 18:06:15 +00:00
Jim Grosbach 3661859214 Re-order test. 
llvm-svn: 139795
 2011-09-15 16:04:13 +00:00
Eli Friedman 888bea0b95 Make demanded-elt simplification for shufflevector slightly stronger. Spotted by inspection. 
llvm-svn: 139768
 2011-09-15 01:14:29 +00:00
Andrew Trick 76a86d3d4c [regcoalescing] bug fix for RegistersDefinedFromSameValue. 
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal.
Fixes PR10920 401.bzip2 miscompile with no IV rewrite.

llvm-svn: 139765
 2011-09-15 01:09:33 +00:00
Jim Grosbach 16680e1d33 Thumb2 assembly parsing and encoding for PLI. 
llvm-svn: 139757
 2011-09-14 23:29:05 +00:00
Jim Grosbach 2e2f6db24b Thumb2 assembly parsing and encoding for PLD. 
llvm-svn: 139756
 2011-09-14 23:26:12 +00:00
Jim Grosbach 801e06b768 Thumb2 assembly parsing and encoding for PKH. 
llvm-svn: 139754
 2011-09-14 23:16:41 +00:00
Owen Anderson d7791b961c Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
llvm-svn: 139747
 2011-09-14 22:46:14 +00:00
Jim Grosbach 61326e08ec Thumb2 assembly parsing and encoding for ORR. 
llvm-svn: 139742
 2011-09-14 21:43:57 +00:00
Jim Grosbach 1fdddf767f Thumb2 assembly parsing and encoding for ORN. 
llvm-svn: 139741
 2011-09-14 21:29:54 +00:00
Jim Grosbach 36acc8e984 Thumb2 assembly parsing and encoding for NOP.W. 
llvm-svn: 139740
 2011-09-14 21:26:25 +00:00
Jim Grosbach 752d6fd529 Thumb2 assembly parsing and encoding for MVN. 
llvm-svn: 139739
 2011-09-14 21:24:41 +00:00
Jim Grosbach 9c8b9932d6 Thumb2 assembly parsing and encoding for MUL. 
llvm-svn: 139735
 2011-09-14 21:00:40 +00:00
Jim Grosbach 0ecd395095 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

llvm-svn: 139721
 2011-09-14 20:03:46 +00:00
Jim Grosbach e9d80bbc1d Thumb2 assembly parsing and encoding for MRC/MRC2/MRRC/MRRC2. 
llvm-svn: 139717
 2011-09-14 19:28:49 +00:00
Jim Grosbach c39c2dfe15 Thumb2 assembly parsing and encoding for MOVT. 
llvm-svn: 139715
 2011-09-14 19:15:15 +00:00
Jim Grosbach 18b8b17579 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

llvm-svn: 139714
 2011-09-14 19:12:11 +00:00
Dan Gohman d4b5e3a4d9 objc_retainBlock is not NoModRef because it can update forwarding pointers 
in memory relevant to the optimizer. rdar://10050579.

llvm-svn: 139708
 2011-09-14 18:13:00 +00:00
Jim Grosbach 3ac26b138b ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573

llvm-svn: 139707
 2011-09-14 18:08:35 +00:00
Nadav Rotem d748dbacb0 Add integer promotion support for vselect 
llvm-svn: 139692
 2011-09-14 14:42:15 +00:00
Craig Topper ee8157cb41 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
llvm-svn: 139691
 2011-09-14 06:41:26 +00:00
Craig Topper 96e00e5a24 Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917. 
llvm-svn: 139690
 2011-09-14 05:55:28 +00:00
Craig Topper 503eef7641 Add test case for PR10851. 
llvm-svn: 139689
 2011-09-14 04:36:54 +00:00
Bruno Cardoso Lopes 333a59eced Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss". 
llvm-svn: 139686
 2011-09-14 02:36:14 +00:00
Devang Patel edc216515e Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective. 
llvm-svn: 139675
 2011-09-14 00:29:50 +00:00
Devang Patel 9cd29103aa Remove unnecessary old test. 
llvm-svn: 139674
 2011-09-14 00:28:54 +00:00
Devang Patel fc9c4a730e Update tests. Remove irrelevant tests. 
llvm-svn: 139658
 2011-09-13 23:07:41 +00:00
Akira Hatanaka 73b5d6ddc1 Delete test cases that generate code for allegrex/psp and cannot be repurposed. 
llvm-svn: 139652
 2011-09-13 22:29:13 +00:00
Owen Anderson 3eb2470eed Make use of Eli's FileCheck sorcery to improve this test. 
llvm-svn: 139645
 2011-09-13 21:37:50 +00:00
Eli Friedman f1518216fd Error out on CodeGen of unaligned load/store. Fix test so it isn't accidentally testing that case. 
llvm-svn: 139641
 2011-09-13 20:50:54 +00:00
Owen Anderson 7f0e98fd7f Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
llvm-svn: 139639
 2011-09-13 20:46:26 +00:00
Akira Hatanaka fba4bd62b1 Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
 2011-09-13 20:13:58 +00:00
Akira Hatanaka f58d6812a9 Disable tests which generate code for allegrex or psp. 
llvm-svn: 139632
 2011-09-13 20:00:35 +00:00
Nadav Rotem 1af0c538e0 update checked pattern 
llvm-svn: 139631
 2011-09-13 19:59:18 +00:00
Nadav Rotem 52202fbf2d Add vselect target support for targets that do not support blend but do support 
xor/and/or (For example SSE2).

llvm-svn: 139623
 2011-09-13 19:17:42 +00:00
Owen Anderson 44ae2da4ec Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
llvm-svn: 139610
 2011-09-13 17:59:19 +00:00
Owen Anderson c3c60a0882 Fix encoding of Thumb2 shifted register operands with RRX shifts. 
llvm-svn: 139606
 2011-09-13 17:34:32 +00:00
Craig Topper e98d8a5c84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
llvm-svn: 139588
 2011-09-13 06:54:58 +00:00
Andrew Trick f9f68b816b [indvars] Revert r139579 until 401.bzip -arch i386 miscompilation is fixed. PR10920. 
llvm-svn: 139583
 2011-09-13 05:23:49 +00:00
Andrew Trick 061d811c51 Disable IV rewriting by default. See PR10916. 
llvm-svn: 139579
 2011-09-13 03:23:21 +00:00
Andrew Trick 5b28cc84f0 Generalize test case to handle multiple indvars modes. 
llvm-svn: 139578
 2011-09-13 03:17:25 +00:00
Andrew Trick 1191773a62 Generalize this test's CHECK statements to handle different indvars modes. 
llvm-svn: 139577
 2011-09-13 02:46:27 +00:00
Andrew Trick 57d8afde93 This test only makes sense with -enable-iv-rewrite. 
llvm-svn: 139576
 2011-09-13 02:45:26 +00:00