c9f4219cfc
Rename MRegisterDesc -> TargetRegisterDesc for consistency
...
llvm-svn: 23564
2005-09-30 17:49:27 +00:00
81f32a2acb
trim down the target info structs now that we have a preferred spill register class for each callee save register
...
Why is V9 maintaining these tables manually? ugh!
llvm-svn: 23561
2005-09-30 17:38:36 +00:00
88025e17c5
constant fold these calls
...
llvm-svn: 23558
2005-09-30 17:16:59 +00:00
bb1c9ecb17
simplify this code using the new regclass info passed in
...
llvm-svn: 23557
2005-09-30 17:12:38 +00:00
8688b92b86
stub out a virtual method
...
llvm-svn: 23554
2005-09-30 06:55:18 +00:00
4984e99b83
CR registers are not used by this "target"
...
llvm-svn: 23552
2005-09-30 06:43:58 +00:00
6169a78f46
these registers don't belong to any register classes, so don't mark them
...
as callee save. They can never be generated by the compiler.
llvm-svn: 23551
2005-09-30 06:42:24 +00:00
33ce5f8a73
Now that self referential classes are supported, get rid of a work-around.
...
llvm-svn: 23544
2005-09-30 04:13:23 +00:00
f6d4173f75
pass extra args
...
llvm-svn: 23539
2005-09-30 01:31:52 +00:00
64ca7cda3f
these methods get extra args
...
llvm-svn: 23538
2005-09-30 01:30:55 +00:00
a654525c1c
Pass extra regclasses into spilling code
...
llvm-svn: 23537
2005-09-30 01:29:42 +00:00
08f157c5b2
Use the 32-bit version for now
...
llvm-svn: 23534
2005-09-30 00:05:05 +00:00
027a2671ef
Add a bunch of patterns for F64 FP ops, add some more integer ops
...
llvm-svn: 23533
2005-09-29 23:34:24 +00:00
1de5706e68
Remove code for patterns that are autogenerated
...
llvm-svn: 23532
2005-09-29 23:33:31 +00:00
a7a83b9255
begining alpha subtarget support
...
llvm-svn: 23531
2005-09-29 22:54:56 +00:00
0a1cd715d4
tblgen autogens this pattern now
...
llvm-svn: 23530
2005-09-29 22:37:24 +00:00
bae1f9d790
copy and paste error
...
llvm-svn: 23528
2005-09-29 21:11:57 +00:00
a748e3ae5b
now that tblgen is smarter, this pattern is not needed. Also, tblgen
...
now inverts commuted versions of ANDC/ORC with the current .td file.
llvm-svn: 23527
2005-09-29 19:29:15 +00:00
02d3ba3db8
consistency with other cases, no functionality change
...
llvm-svn: 23524
2005-09-29 17:38:52 +00:00
eca4f56646
Make the JIT default to the DAG isel instead of the pattern isel, like LLC.
...
The Pattern isel has some strange memory corruption issues going on. :(
This should have been converted over anyway, but it got forgotten somehow
when switching to the dag isel.
llvm-svn: 23523
2005-09-29 17:31:03 +00:00
08c319fbdd
Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.
...
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.
llvm-svn: 23515
2005-09-29 00:59:32 +00:00
d4e9e8b7ec
Codegen ADD X, IMM -> addis/addi if needed.
...
This implements PowerPC/fold-li.ll
llvm-svn: 23514
2005-09-28 23:07:13 +00:00
b9b2e77295
Autogen MUL, move FP cases together
...
llvm-svn: 23512
2005-09-28 22:53:16 +00:00
5769311c92
disentangle FP from INT versions of div/mul
...
llvm-svn: 23511
2005-09-28 22:50:24 +00:00
585131baaf
Use the autogenerated matcher for ADD/SUB
...
llvm-svn: 23510
2005-09-28 22:47:28 +00:00
f023b2cda2
add a patter for SUBFIC
...
llvm-svn: 23509
2005-09-28 22:47:06 +00:00
21551ea5ab
Mark int binops as int-only, add FP binops. Mark FADD/FMUL as commutative but
...
not associative. Add [SU]REM.
llvm-svn: 23508
2005-09-28 22:38:27 +00:00
d3ea19b51a
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
llvm-svn: 23506
2005-09-28 22:29:58 +00:00
0815dcae3f
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
llvm-svn: 23505
2005-09-28 22:29:17 +00:00
7fe6734dff
Mark associative nodes as associative
...
llvm-svn: 23503
2005-09-28 20:58:39 +00:00
b97b054ba7
Nate pointed out that mulh[us] are commutative as well. Thanks!
...
llvm-svn: 23500
2005-09-28 19:01:44 +00:00
89d168ceb3
expose commutativity information
...
llvm-svn: 23498
2005-09-28 18:27:58 +00:00
fab48b3285
All (xor *) cases are autogenerated now
...
llvm-svn: 23497
2005-09-28 18:12:37 +00:00
037d69a404
add support for missed eqv tests
...
llvm-svn: 23496
2005-09-28 18:10:51 +00:00
33f8e08c8f
Implement PowerPC/eqv-andc-orc-nor.ll:EQV3
...
llvm-svn: 23494
2005-09-28 18:04:52 +00:00
8cd7b88a88
learn to codegen not as NOR instead of xoris/xori
...
llvm-svn: 23490
2005-09-28 17:13:15 +00:00
bb5939a436
These nodes are all autogenerated
...
llvm-svn: 23489
2005-09-28 17:07:09 +00:00
a028e7a39c
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
...
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
llvm-svn: 23482
2005-09-27 22:18:25 +00:00
59dc1e082c
initialize new flag
...
llvm-svn: 23480
2005-09-27 22:13:56 +00:00
5635cc069f
fix CBackend/2005-09-27-VolatileFuncPtr.ll
...
llvm-svn: 23475
2005-09-27 20:52:44 +00:00
c628f00845
Make sure to clear the CodeGenMap after each basic block is selected to avoid
...
cross MBB pollution.
llvm-svn: 23470
2005-09-27 17:45:33 +00:00
54ec5f2089
Move the post-lsr simplify cfg pass after lowereh, so it can clean up after
...
eh lowering as well.
llvm-svn: 23459
2005-09-27 00:14:41 +00:00
4435b149a0
minor pattern shuffling
...
llvm-svn: 23458
2005-09-26 22:20:16 +00:00
6736a6cdd2
Teach the dag isel generator how to construct arbitrary immediates. The
...
generated isel now tries li then lis, then lis+ori.
llvm-svn: 23418
2005-09-24 00:41:58 +00:00
de3c87a2ab
Implement the isLoadFromStackSlot interface
...
llvm-svn: 23387
2005-09-19 05:23:44 +00:00
4d9cf68023
Implement hook for ppc
...
llvm-svn: 23374
2005-09-17 01:03:26 +00:00
0ebec06671
disable this for now
...
llvm-svn: 23366
2005-09-15 21:44:00 +00:00
9e4a4ee3dc
Give all operands names
...
llvm-svn: 23357
2005-09-14 21:11:13 +00:00
2e84be22a8
give all operands names
...
llvm-svn: 23356
2005-09-14 21:10:24 +00:00
f006d15e7f
Fix some issues exposed by more testing. XORIS had the wrong operands
...
specified. The various *imm operands defined by PPC are really all i32,
even though the actual immediate is restricted to a smaller value in it.
llvm-svn: 23352
2005-09-14 20:53:05 +00:00
6b013fc923
Fix some bugs noticed by new checking code
...
llvm-svn: 23350
2005-09-14 18:18:39 +00:00
b42e962d23
fix a major regression from my patch this afternoon
...
llvm-svn: 23347
2005-09-14 06:06:45 +00:00
b011cb2746
we don't need this proto any longer
...
llvm-svn: 23342
2005-09-13 22:05:21 +00:00
03e08eefc7
move the #include for the generated code into the isel class body so we
...
can use/define class methods
llvm-svn: 23339
2005-09-13 22:03:06 +00:00
0f965a615e
Change the arg lowering code to use copyfromreg from vregs associated
...
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
llvm-svn: 23334
2005-09-13 19:33:40 +00:00
ee8113293e
This has been moved to the target-indep code
...
llvm-svn: 23333
2005-09-13 19:32:18 +00:00
fb96e50b8c
This code is no longer needed, it is moved to the target-indep code
...
llvm-svn: 23332
2005-09-13 19:31:44 +00:00
64685b4ca2
Majik numbers are bad
...
llvm-svn: 23330
2005-09-13 19:03:13 +00:00
aa6cbd90c5
Remove some dead vectors
...
llvm-svn: 23329
2005-09-13 18:47:49 +00:00
4309c3a785
PowerPC cannot truncstore i1 natively
...
llvm-svn: 23304
2005-09-10 00:21:06 +00:00
0f2146bb5d
I forgot that we always spill fp values as 64-bits. Implement spill folding
...
for FP as well. This triggers a couple dozen times on 177.mesa (for example).
llvm-svn: 23299
2005-09-09 21:59:44 +00:00
712e78ee28
Fix a problem that Nate noticed, where spill code was not getting coallesced
...
with copies, leading to code like this:
lwz r4, 380(r1)
or r10, r4, r4 ;; Last use of r4
By teaching the PPC backend how to fold spills into copies, we now get this
code:
lwz r10, 380(r1)
wow. :)
This reduces a testcase nate sent me from 1505 instructions to 1484.
Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch
llvm-svn: 23298
2005-09-09 21:46:49 +00:00
f540c1a2e8
code cleanup
...
llvm-svn: 23297
2005-09-09 20:51:08 +00:00
c37a2f13c4
Teach the code generator that rlwimi is commutable if the rotate amount
...
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
llvm-svn: 23292
2005-09-09 18:17:41 +00:00
39b4d83f6a
Introduce two new concepts:
...
1. Add support for defining Pattern's, which can match expressions when there
is no instruction that directly implements something. Instructions usually
implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
This seperates the concept of a node xform out from the existing predicate
support.
Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.
llvm-svn: 23286
2005-09-09 00:39:56 +00:00
4b09f3c6f5
whitespace/comment changes, no functionality diffs
...
llvm-svn: 23283
2005-09-08 23:17:26 +00:00
0ec8fa0880
Add a bunch of stuff needed for node type inference. Move 'BLR' down with
...
the rest of the instructions, add comment markers to seperate portions of
the file into logical parts
llvm-svn: 23277
2005-09-08 19:50:41 +00:00
76cb006e2c
add patterns for x?oris?
...
llvm-svn: 23268
2005-09-08 17:40:49 +00:00
2d8032b54c
add patterns to the addi/addis/mulli etc instructions. Define predicates
...
for matching signed 16-bit and shifted 16-bit ppc immediates
llvm-svn: 23267
2005-09-08 17:33:10 +00:00
cf9b0e6673
Add patterns for some new instructions, allowing the use of the ineg fragment.
...
llvm-svn: 23266
2005-09-08 17:01:54 +00:00
7c8dba750c
ignore generated files
...
llvm-svn: 23263
2005-09-07 23:47:44 +00:00
498915dafa
Remove some cases handled by the generated portion of the isel
...
llvm-svn: 23262
2005-09-07 23:45:15 +00:00
5ea0ee7b19
On non-apple systems, when using -march=ppc32, do not print:
...
'' is not a recognized processor for this target (ignoring processor)
Default to "generic" instead of "" for the default CPU.
llvm-svn: 23257
2005-09-07 05:45:33 +00:00
8d0e9d90aa
Print:
...
'' is not a recognized processor for this target (ignoring processor)
instead of:
is not a recognized processor for this target (ignoring processor)
llvm-svn: 23256
2005-09-07 05:44:14 +00:00
6095214bf0
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
...
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
llvm-svn: 23250
2005-09-06 22:03:27 +00:00
a63a066205
Fix up the AssertXext problem, as well as adding it at calls
...
llvm-svn: 23246
2005-09-06 17:00:23 +00:00
e9e2c6d314
Add note about future optimization noted in the ppc compiler writer's guide
...
llvm-svn: 23245
2005-09-06 15:30:48 +00:00
2dded8302a
Add accessor for 64bit flag, so that we can tell when it is safe to
...
generate the fun in-register fp<->long instructions.
llvm-svn: 23244
2005-09-06 15:30:12 +00:00
c8bd5bda59
revert part of the last change, should fix regressions
...
llvm-svn: 23241
2005-09-04 06:12:19 +00:00
aa833d4571
explicitly specify an operands list for patterns with inputs (e.g. neg)
...
llvm-svn: 23240
2005-09-03 01:28:40 +00:00
8ae9525bd0
include the dag isel fragment
...
llvm-svn: 23239
2005-09-03 01:17:22 +00:00
0442dcfabc
ask for a dag isel
...
llvm-svn: 23238
2005-09-03 01:15:41 +00:00
5f12cf14be
Change the isel to not break out of the big giant switch. Instead, the
...
switch should never be exited, so its bottom is now unreachable.
llvm-svn: 23234
2005-09-03 00:53:47 +00:00
9220f92c41
rearrange logical ops to group them together more consistently.
...
Define the PatFrag class which can be used to define subpatterns to match
things with. Define 'not', and use it to define the patterns for andc,
nand, etc.
llvm-svn: 23233
2005-09-03 00:21:51 +00:00
dcbb561b76
Add AND/OR/XOR
...
llvm-svn: 23232
2005-09-02 22:35:53 +00:00
3a1002d529
Add some initial patterns to simple binary instructions, though they
...
currently don't do anything. This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.
This patch also removes PPC::SUB, because it is dead.
llvm-svn: 23230
2005-09-02 21:18:00 +00:00
06e237f253
turn on dag isel by default
...
llvm-svn: 23226
2005-09-02 19:53:54 +00:00
27d628dfc9
Add help support for -mcpu and -mattr.
...
llvm-svn: 23222
2005-09-02 19:27:43 +00:00
9690a4f321
Pull out Lowering in preperation for multiple ISels. Oh, and get rid of some stuff
...
llvm-svn: 23220
2005-09-02 18:46:02 +00:00
aa3b1fcc58
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
...
Remove the -enable-gpopt option which is subsumed by feature flags.
llvm-svn: 23218
2005-09-02 18:33:05 +00:00
a6dde9962d
Fix VC++ build errors
...
llvm-svn: 23210
2005-09-02 02:51:42 +00:00
763a3a0fa7
Restore this patch now that the latent bug has been fixed
...
llvm-svn: 23209
2005-09-02 01:24:55 +00:00
06d440f2ee
Revert the previous patch which causes a mysterious regression in toast.
...
llvm-svn: 23207
2005-09-02 00:47:05 +00:00
210975cfbb
Handle any_extend like zext
...
llvm-svn: 23202
2005-09-02 00:16:09 +00:00
2493f0e5fd
Handle ANY_EXTEND like ZERO_EXTEND. Simplify the extend/truncate code on
...
the observation that it only has to handle i1 -> i64 and i64 -> i1.
llvm-svn: 23201
2005-09-02 00:15:30 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
...
the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
68d15fdfea
Align functions to 16-byte boundaries, to eliminate noise in performance measurements. This improves the performance of 'treeadd' by about 20% with the dag
...
isel, restoring it to the pattern-isel level (which happens to get the alignment right).
llvm-svn: 23194
2005-09-01 23:08:50 +00:00
e40a3ccd60
Local labels on darwin apparently start with just 'L', not .L like other
...
platforms. This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)
llvm-svn: 23193
2005-09-01 21:48:35 +00:00
19058c3989
1. Use SubtargetFeatures in llc/lli.
...
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
llvm-svn: 23192
2005-09-01 21:38:21 +00:00
3fee6a51a9
This new class provides support for platform specific "features". The intent
...
is to manage processor specific attributes from the command line. See examples
of use in llc/lli and PowerPCTargetSubtarget.
llvm-svn: 23191
2005-09-01 21:36:18 +00:00
a305d28cf6
Implement dynamic allocas correctly. In particular, because we were copying
...
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
llvm-svn: 23190
2005-09-01 21:31:30 +00:00
293b3a68e0
Fix a bug where we were useing HA to get the high part, which seems like it
...
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
llvm-svn: 23189
2005-09-01 19:38:28 +00:00
34182aff7f
Do not select the operands being passed into SelectCC. IT does this itself
...
and selecting early prevents folding immediates into the cmpw* instructions
llvm-svn: 23188
2005-09-01 19:20:44 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
6bad1fb19e
Remove dead code
...
llvm-svn: 23179
2005-08-31 20:25:15 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
3a04a4b767
Remove code that is now dead from the pattern isel.
...
llvm-svn: 23177
2005-08-31 19:11:36 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
2bd2af8ecd
add assert zext/sext to the dag isel
...
llvm-svn: 23171
2005-08-31 18:08:46 +00:00
46ff6aa993
Handle AssertSext/AssertZext nodes, fixing the regressions last night.
...
llvm-svn: 23170
2005-08-31 17:48:04 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
f4d594370b
Fix 'ret long' to return the high and lo parts in the right registers. This
...
fixes crafty and probably others.
llvm-svn: 23167
2005-08-31 01:34:29 +00:00
69e9a9a94c
now that physregs can exist in the same dag with multiple types, remove some
...
ugly hacks
llvm-svn: 23162
2005-08-30 22:59:48 +00:00
8f8d539746
Fix type mismatches when passing f32 values to calls
...
llvm-svn: 23159
2005-08-30 21:28:19 +00:00
9f23ae226f
Fix some indentation (first hunks).
...
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
llvm-svn: 23155
2005-08-30 18:37:48 +00:00
6a41fd75cd
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
...
fixes fourinarow
llvm-svn: 23153
2005-08-30 17:42:59 +00:00
bdf3d3defb
codegen ADD_PARTS correctly: put the results in the right registers! This
...
fixes fhourstones
llvm-svn: 23152
2005-08-30 17:40:13 +00:00
45706e9fb8
add operands in the right order, fixing McCat/18-imp with the dag isel
...
llvm-svn: 23150
2005-08-30 17:13:58 +00:00
7a59b1cf90
Make sure the selector emits register register copies with flag operands
...
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
llvm-svn: 23143
2005-08-30 01:57:02 +00:00
e413b60632
The first operand to AND does not always have more than two operands. This
...
fixes MediaBench/toast with the dag selector
llvm-svn: 23141
2005-08-30 00:59:16 +00:00
e75b5e63a7
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
...
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
2005-08-30 00:45:18 +00:00
61f7c3e843
emit FMR instructions to convert f64<->f32 instructions, so things like
...
STOREs, know the right type to store.
llvm-svn: 23139
2005-08-30 00:30:43 +00:00
62b9a5d1f8
Fix some really strange indentation that xcode likes to use.
...
no xcode, this is not right:
if (!foo) break;
X;
llvm-svn: 23138
2005-08-30 00:19:00 +00:00
12357281b8
fix a crash in cfrac
...
llvm-svn: 23137
2005-08-29 23:49:25 +00:00
1cbbe1015a
Implement DYNAMIC_STACKALLOC, wrap some long lines
...
llvm-svn: 23136
2005-08-29 23:30:11 +00:00
b2b418509b
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
...
This fixes voronoi and bh in Olden, allowing all of olden to pass!
llvm-svn: 23133
2005-08-29 22:22:57 +00:00
c429ab2fb1
Fix a bug the last patch exposed in treeadd among others
...
llvm-svn: 23127
2005-08-29 01:07:02 +00:00
d4d683a47b
A hack to fix a problem folding immedaites. This fixes Olden/power.
...
llvm-svn: 23126
2005-08-29 01:01:01 +00:00
3ccad3fb8c
Fix order of operands for copytoreg node when emitting calls. This fixes
...
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
llvm-svn: 23125
2005-08-29 00:26:57 +00:00
66ddc8d3bf
add operands in the correct order
...
llvm-svn: 23123
2005-08-29 00:02:01 +00:00
dfcde88d07
Fix a bug in FP_EXTEND, implement FP_TO_SINT
...
llvm-svn: 23121
2005-08-28 23:59:09 +00:00
38660c6666
fix an assertion failure in treeadd
...
llvm-svn: 23120
2005-08-28 23:39:22 +00:00
aa7fbca285
Adjust to member variable name change.
...
llvm-svn: 23119
2005-08-27 19:09:48 +00:00
85d93a3ec9
Change the names of member variables per Chris' instructions, and document
...
them more clearly.
llvm-svn: 23118
2005-08-27 19:09:02 +00:00
787e962795
The condition register being branched on may not be cr0, as such, print it.
...
This fixes: UnitTests/2005-07-17-INT-To-FP.c
llvm-svn: 23112
2005-08-26 23:42:05 +00:00
29bfaa7ef0
Propagate cr# from COND_BRANCH to the actual branch instruction as appropriate
...
llvm-svn: 23111
2005-08-26 23:41:27 +00:00
422e23dd02
allow code using mtcrf to assemble
...
llvm-svn: 23107
2005-08-26 22:05:54 +00:00
72f23815bc
Remove operand type 'crbit', since it is no longer used
...
llvm-svn: 23106
2005-08-26 22:04:17 +00:00
c3d1bdd0a9
teach getClass what a condition reg is
...
llvm-svn: 23105
2005-08-26 21:51:29 +00:00
97345405a6
Minor cleanups:
...
* avoid calling getClass() multiple times (it is relatively expensive)
* Allow -disable-fp-elim to turn of frame pointer elimination.
llvm-svn: 23104
2005-08-26 21:49:18 +00:00
9b577f108a
implement SELECT_CC fully for the DAG->DAG isel!
...
llvm-svn: 23101
2005-08-26 21:23:58 +00:00
c6a0338c04
spell this right
...
llvm-svn: 23099
2005-08-26 20:55:40 +00:00
0081dfa91e
Add a flag
...
llvm-svn: 23092
2005-08-26 20:29:01 +00:00
b2854fadda
Make fsel emission work with both the pattern and dag-dag selectors, by
...
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
llvm-svn: 23091
2005-08-26 20:25:03 +00:00
bec817ce6f
implement the fold for:
...
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
llvm-svn: 23089
2005-08-26 18:46:49 +00:00
a9e6a82d66
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
...
just return its input, instead of emitting an explicit copy.
llvm-svn: 23088
2005-08-26 18:37:23 +00:00
76eea9a480
Remove some code made dead by the fsel patch
...
llvm-svn: 23085
2005-08-26 17:45:06 +00:00
c75e047245
now that fsel is formed during legalization, this code is dead
...
llvm-svn: 23084
2005-08-26 17:40:39 +00:00
7f1fa8eaef
implement the other half of the select_cc -> fsel lowering, which handles
...
when the RHS of the comparison is 0.0. Turn this on by default.
llvm-svn: 23083
2005-08-26 17:36:52 +00:00
d0dc6f4299
Fix a bug in my previous checkin
...
llvm-svn: 23082
2005-08-26 17:18:44 +00:00
c30405e0ee
Change ConstantPoolSDNode to actually hold the Constant itself instead of
...
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
llvm-svn: 23081
2005-08-26 17:15:30 +00:00
7bbdae53d6
Fix some warnings in an optimized build
...
llvm-svn: 23080
2005-08-26 16:38:51 +00:00
2091a36631
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
...
every other SD API. Fix it to take the opcode before the types.
llvm-svn: 23079
2005-08-26 16:36:26 +00:00
7b809f593b
Fix JIT encoding of conditional branches
...
llvm-svn: 23076
2005-08-26 04:11:42 +00:00
f3d06c6417
add initial support for converting select_cc -> fsel in the legalizer
...
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
llvm-svn: 23075
2005-08-26 00:52:45 +00:00
89093ca62a
SUBFIC produces two results, not one.
...
llvm-svn: 23073
2005-08-26 00:34:06 +00:00
bed4f2b982
Implement SHL_PARTS and SRL_PARTS
...
llvm-svn: 23072
2005-08-26 00:28:00 +00:00
b81431b012
Emit the lo/hi parts in the right order :)
...
llvm-svn: 23068
2005-08-25 23:36:49 +00:00
02884fe41c
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
...
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
llvm-svn: 23066
2005-08-25 23:21:06 +00:00
abbd8ea048
simplify the add/sub_parts code
...
llvm-svn: 23065
2005-08-25 23:19:58 +00:00
6e184f2b3d
Finish implementing SDIV/UDIV by copying over the majik constant code from
...
ISelPattern
llvm-svn: 23062
2005-08-25 22:04:30 +00:00
717f97a5c8
Simplify some code. It's not clear why the UDIV expanded sequence
...
doesn't work for large uint constants, but we'll keep the current behavior
llvm-svn: 23061
2005-08-25 22:03:50 +00:00
b746dd1cf6
Implement setcc correctly for G5 and non-G5 systems
...
llvm-svn: 23060
2005-08-25 21:39:42 +00:00
3dcd75bc54
implement setcc on the G5. We're still missing the non-g5 specific bits, but
...
they will come later.
llvm-svn: 23059
2005-08-25 20:08:18 +00:00
65ffd8fbf4
Remove option to make SetCC illegal on PowerPC after long discussion with
...
Chris. This will be accomplished through correctly modeling CR's and
subregs.
llvm-svn: 23056
2005-08-25 20:01:10 +00:00
dc66457022
Add support for sdiv by 2^k and -2^k. Producing code like:
...
_test:
srawi r2, r3, 2
addze r3, r2
blr
llvm-svn: 23052
2005-08-25 17:50:06 +00:00
4bd2aab6c1
fit in 80 cols
...
llvm-svn: 23051
2005-08-25 17:49:31 +00:00
d24ad52efa
add an enum value
...
llvm-svn: 23048
2005-08-25 17:07:09 +00:00
25db699671
Implement support for taking the address of constant pool indices, which
...
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
llvm-svn: 23042
2005-08-25 05:04:11 +00:00
666512c832
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
...
llvm-svn: 23038
2005-08-25 04:47:18 +00:00
e4c338d0d8
Fully implement frame index, so that we can pass the address of alloca's
...
around to functions and stuff
llvm-svn: 23036
2005-08-25 00:45:43 +00:00
66a6a13225
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
...
llvm-svn: 23034
2005-08-25 00:29:58 +00:00
4ae278a760
LFS/STFS load and store FP values, not integer ones. This change allows us
...
to codegen this: float foo() { return 1.245; }
into this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs f1, lo16(.CPI_foo_0)(r2)
blr
instead of this:
_foo:
lis r2, ha16(.CPI_foo_0)
lfs r2, lo16(.CPI_foo_0)(r2) <-- ouch
or f1, r2, r2 <-- ouch
blr
with the dag isel.
llvm-svn: 23033
2005-08-25 00:26:22 +00:00
794eb6684d
Fix a broken assertion
...
llvm-svn: 23032
2005-08-25 00:19:12 +00:00
c146940f0d
Fix a warning
...
llvm-svn: 23031
2005-08-25 00:05:15 +00:00
daae1e10f7
fix a warning in optimized build
...
llvm-svn: 23030
2005-08-25 00:03:21 +00:00
751c6c3944
Fix some warnings
...
llvm-svn: 23029
2005-08-25 00:00:26 +00:00
a3fbdae515
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
...
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
llvm-svn: 23028
2005-08-24 23:08:16 +00:00
d83cd354bd
implement support for calls
...
llvm-svn: 23026
2005-08-24 22:45:17 +00:00
1fc2a7f006
Remove some dead cases.
...
Emit the indcall sequence as:
mtctr inreg
mr R12, inreg
btctr
If inreg and R12 aren't coallesced, this reduces the odds of having the mtctr
and btctr in the same dispatch group. :)
llvm-svn: 23023
2005-08-24 22:21:47 +00:00
1e98a330f2
add an idea
...
llvm-svn: 23020
2005-08-24 18:15:24 +00:00
ade525491f
Adjust to new interface
...
llvm-svn: 23010
2005-08-24 16:34:12 +00:00
7c1ba938be
Whoops, fix a thinko. All cases except SETNE are now handled by the
...
target independent code in SelectionDAG.cpp
llvm-svn: 23002
2005-08-24 05:06:48 +00:00
a1e0a2f72b
Remove unused statistic
...
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
llvm-svn: 23001
2005-08-24 05:03:20 +00:00
6948b79b26
Add the "ppc specific" setcc-equivalent select_cc cases
...
Prefer 'neg X' to 'subfic 0, X' since it does not set XER[CA]
llvm-svn: 23000
2005-08-24 04:59:21 +00:00
b6d034a841
Add callseq_begin/end support
...
Call stil not supported yet
llvm-svn: 22998
2005-08-24 00:47:15 +00:00
cdc0cbbcd0
Adjust to new livevars interface
...
llvm-svn: 22991
2005-08-23 23:41:14 +00:00
7c1c6e06f3
Simplify this code by using LiveVariables::KillsRegister
...
llvm-svn: 22988
2005-08-23 22:49:55 +00:00
9c0a243ce5
Fix PR618 and Regression/CodeGen/CBackend/2005-08-23-Fmod.ll by not emitting
...
x%y for 'rem' on fp values.
llvm-svn: 22984
2005-08-23 20:22:50 +00:00
5e3953d761
add a note
...
llvm-svn: 22982
2005-08-23 06:27:59 +00:00
f3ce09b36e
Ack, typo
...
llvm-svn: 22981
2005-08-23 05:45:10 +00:00
7216ad415b
Add an option to make SetCC illegal as a beta option
...
llvm-svn: 22979
2005-08-23 05:42:36 +00:00
06436b2b7d
Remove some instructions we no longer generate
...
llvm-svn: 22976
2005-08-23 01:16:46 +00:00
46323cf0e2
Remove some regs that are not used.
...
llvm-svn: 22975
2005-08-22 22:32:13 +00:00
956820d989
Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString
...
in the asmprinter. This changes the .td files to use lower case register names,
avoiding the need to do this call. This speeds up the asmprinter from 1.52s
to 1.06s on kc++ in a release build.
llvm-svn: 22974
2005-08-22 22:00:02 +00:00
d2f2aff484
Fix a crash I introduced into the IA64 backend with my copyfromreg change.
...
It used to crash on any function that took float arguments.
llvm-svn: 22973
2005-08-22 21:33:11 +00:00
9d46518e5c
Add a pass name for -time-passes output
...
llvm-svn: 22970
2005-08-22 18:28:09 +00:00
ca0c0d7550
Implement stores.
...
llvm-svn: 22963
2005-08-22 01:27:59 +00:00
1d634b2f44
Fix compilation of:
...
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
llvm-svn: 22961
2005-08-22 00:59:14 +00:00
b676e5a666
Make sure expressions only have one use before emitting them into a place that is conditionally executed
...
llvm-svn: 22960
2005-08-22 00:47:28 +00:00
Chris Lattner