Commit Graph

303229 Commits

Author SHA1 Message Date
Fangrui Song d8fd0ec032 [AsmPrinter] Rename a comment of .debug_gnu_pubnames entry
Summary:
The comment refers to the field as "Kind:". However, in gdb,

https://sourceware.org/gdb//onlinedocs/gdb/Index-Section-Format.html names it "attributes",
gdb/dwarf2read.c:dw2_symtab_iter_next refers to the whole value as "cu_index_and_attrs"

Change it to `Attributes:` for consistency.

Reviewers: dblaikie

Reviewed By: dblaikie

Subscribers: aprantl, JDevlieghere, arphaman, llvm-commits

Differential Revision: https://reviews.llvm.org/D54480

llvm-svn: 346790
2018-11-13 20:18:08 +00:00
David Blaikie 27692de9cf DebugInfo: Add a driver flag for DWARF debug_ranges base address specifier use.
Summary:
This saves a lot of relocations in optimized object files (at the cost
of some cost/increase in linked executable bytes), but gold's 32 bit
gdb-index support has a bug (
https://sourceware.org/bugzilla/show_bug.cgi?id=21894 ) so we can't
switch to this unconditionally. (& even if it weren't for that bug, one
might argue that some users would want to optimize in one direction or
the other - prioritizing object size or linked executable size)

Differential Revision: https://reviews.llvm.org/D54243

llvm-svn: 346789
2018-11-13 20:08:13 +00:00
David Blaikie bb279116f2 DebugInfo: Add a CU metadata attribute for use of DWARF ranges base address specifiers
Summary:
Ranges base address specifiers can save a lot of object size in
relocation records especially in optimized builds.

For an optimized self-host build of Clang with split DWARF and debug
info compression in object files, but uncompressed debug info in the
executable, this change produces about 18% smaller object files and 6%
larger executable.

While it would've been nice to turn this on by default, gold's 32 bit
gdb-index support crashes on this input & I don't think there's any
perfect heuristic to implement solely in LLVM that would suffice - so
we'll need a flag one way or another (also possible people might want to
aggressively optimized for executable size that contains debug info
(even with compression this would still come at some cost to executable
size)) - so let's plumb it through.

Differential Revision: https://reviews.llvm.org/D54242

llvm-svn: 346788
2018-11-13 20:08:10 +00:00
Zachary Turner 2af3416618 [NativePDB] Add support for S_CONSTANT records.
clang-cl does not emit these, but MSVC does, so we need to be able to
handle them.

Because clang-cl does not generate them, it was a bit hard to write a
test. So what I had to do was get an PDB file with some S_CONSTANT
records in using cl and link, dump it using llvm-pdbutil dump -globals
-sym-data to get the bytes of the records, generate the same object file
using clang-cl but with -S to emit an assembly file, and replace all the
S_LDATA32 records with the bytes of the S_CONSTANT records. This way, we
can compile the file using llvm-mc and link it with lld-link.

Differential Revision: https://reviews.llvm.org/D54452

llvm-svn: 346787
2018-11-13 20:07:57 +00:00
Zachary Turner 03a24052f3 [NativePDB] Improved support for nested type reconstruction.
In a previous patch, we pre-processed the TPI stream in order to build
the reverse mapping from nested type -> parent type so that we could
accurately reconstruct a DeclContext hierarchy.

However, there were some issues. An LF_NESTTYPE record is really just a
typedef, so although it happens to be used to indicate the name of the
nested type and referring to the global record which defines the type,
it is also used for every other kind of nested typedef. When we rebuild
the DeclContext hierarchy, we want it to be as accurate as possible,
which means that if we have something like:

  struct A {
    struct B {};
    using C = B;
  };

We don't want to create two CXXRecordDecls in the AST each with the
exact same definition. We just want to create one for B and then
define C as an alias to B. Previously, however, it would not be able
to distinguish between the two cases and it would treat A::B and
A::C as being two classes each with separate definitions. We address
the first half of improving the pre-processing logic so that only
actual definitions are treated this way.

Later, in a followup patch, we can handle the case of nested
typedefs since we're already going to be enumerating the field list
anyway and this patch introduces the general framework for
distinguishing between the two cases.

Differential Revision: https://reviews.llvm.org/D54357

llvm-svn: 346786
2018-11-13 20:07:32 +00:00
Matt Arsenault c2728bc932 Add fneg instruction to syntax highlighting lists
llvm-svn: 346785
2018-11-13 19:50:38 +00:00
Craig Topper aca8390216 [SelectionDAG][X86] Relax restriction on the width of an input to *_EXTEND_VECTOR_INREG. Use them and regular *_EXTEND to replace the X86 specific VSEXT/VZEXT opcodes
Previously, the extend_vector_inreg opcode required their input register to be the same total width as their output. But this doesn't match up with how the X86 instructions are defined. For X86 the input just needs to be a legal type with at least enough elements to cover the output.

This patch weakens the check on these nodes and allows them to be used as long as they have more input elements than output elements. I haven't changed type legalization behavior so it will still create them with matching input and output sizes.

X86 will custom legalize these nodes by shrinking the input to be a 128 bit vector and once we've done that we treat them as legal operations. We still have one case during type legalization where we must custom handle v64i8 on avx512f targets without avx512bw where v64i8 isn't a legal type. In this case we will custom type legalize to a *extend_vector_inreg with a v16i8 input. After that the input is a legal type so type legalization should ignore the node and doesn't need to know about the relaxed restriction. We are no longer allowed to use the default expansion for these nodes during vector op legalization since the default expansion uses a shuffle which required the widths to match. Custom legalization for all types will prevent us from reaching the default expansion code.

I believe DAG combine works correctly with the released restriction because it doesn't check the number of input elements.

The rest of the patch is changing X86 to use either the vector_inreg nodes or the regular zero_extend/sign_extend nodes. I had to add additional isel patterns to handle any_extend during isel since simplifydemandedbits can create them at any time so we can't legalize to zero_extend before isel. We don't yet create any_extend_vector_inreg in simplifydemandedbits.

Differential Revision: https://reviews.llvm.org/D54346

llvm-svn: 346784
2018-11-13 19:45:21 +00:00
Davide Italiano cdcfa5d07f [Cocoa] Implement formatter for the new NSDate representation.
<rdar://problem/46002786>

llvm-svn: 346783
2018-11-13 19:43:43 +00:00
Jordan Rupprecht c5bae7834e [llvm-objcopy] Rename --keep to --keep-section.
Summary:
llvm-objcopy/strip support `--keep` (for sections) and `--keep-symbols` (for symbols). For consistency and clarity, rename `--keep` to `--keep-section`.
In fact, for GNU compatability, -K is --keep-symbol, so it's weird that the alias `-K` is not the same as the short-ish `--keep`.

Reviewers: jakehehrlich, jhenderson, alexshap, MaskRay, espindola

Reviewed By: jakehehrlich, MaskRay

Subscribers: emaste, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D54477

llvm-svn: 346782
2018-11-13 19:32:27 +00:00
Bruno Ricci 69396af194 [AST][NFC] Style fixes for UnaryOperator
In preparation for the patch which will move some data to the bit-fields
of Stmt. In particular, rename the private variable "Val" -> "Operand"
since the substatement is the operand of the unary operator.
Run clang-format on UnaryOperator. NFC otherwise.

llvm-svn: 346781
2018-11-13 19:27:39 +00:00
Jonas Devlieghere 9e046f02e3 Add GDB remote packet reproducer.
llvm-svn: 346780
2018-11-13 19:18:16 +00:00
Eric Fiselier 3bea50aeb3 Fix UB in string.bench.cpp.
The usage of aligned_storage failed to pass the alignment it wanted,
which caused it to have a larger size and alignment that the
std::string's it was intended to store.

This patch manually specifies the alignment, as well as cleaning up
type alias bugs.

llvm-svn: 346779
2018-11-13 19:16:19 +00:00
Sam Clegg f98ba05f3d [WebAssembly] Fix broken assumption that all bitcasts are to functions types
Specifically, we can bitcast to void.

Fixes PR39591

Differential Revision: https://reviews.llvm.org/D54447

llvm-svn: 346778
2018-11-13 19:14:02 +00:00
Reid Kleckner 551acf03dc [COFF] Simplify relocation to discarded section diagnostic code, NFC
Move it out of the loop that applies relocations for readability.

llvm-svn: 346777
2018-11-13 18:30:31 +00:00
Jonas Devlieghere b23f430ec9 [FileSystem] Add expand_tilde function
In D54435 there was some discussion about the expand_tilde flag for
real_path that I wanted to expose through the VFS. The consensus is that
these two things should be separate functions. Since we already have the
code for this I went ahead and added a function expand_tilde that does
just that.

Differential revision: https://reviews.llvm.org/D54448

llvm-svn: 346776
2018-11-13 18:23:32 +00:00
Jim Ingham 7716ddf18d Since ABI's now hold a process WP, they should be handed
out one per process rather than keeping a single global instance.

Differential Revision: https://reviews.llvm.org/D54460

llvm-svn: 346775
2018-11-13 18:18:32 +00:00
Cameron McInally cbde0d9c7b [IR] Add a dedicated FNeg IR Instruction
The IEEE-754 Standard makes it clear that fneg(x) and
fsub(-0.0, x) are two different operations. The former is a bitwise
operation, while the latter is an arithmetic operation. This patch
creates a dedicated FNeg IR Instruction to model that behavior.

Differential Revision: https://reviews.llvm.org/D53877

llvm-svn: 346774
2018-11-13 18:15:47 +00:00
Simon Atanasyan 9d87256d3d [WebAssembly] Mark immediates.ll as XFAILed on MIPS hosts
Usually MIPS hosts uses a legacy (non IEEE 754-2008) encoding for NaNs.
Tests like `nan_f32` failed in attempt to compare hard-coded IEEE
754-2008 NaN value and a legacy NaN value provided by a system.

llvm-svn: 346773
2018-11-13 18:14:29 +00:00
Marshall Clow 78d8b5e1cf Remove duplicate entry for issue 3134
llvm-svn: 346772
2018-11-13 18:07:51 +00:00
Marshall Clow 04fc84408b Update status for issue 3122
llvm-svn: 346771
2018-11-13 18:05:10 +00:00
Bruno Ricci a795e8012e [AST][NFC] Pack DeclRefExpr
Move the SourceLocation to the bit-fields of Stmt + clang-format.
This saves one pointer per DeclRefExpr but otherwise NFC.

llvm-svn: 346770
2018-11-13 17:56:44 +00:00
Florian Hahn 107d0a8756 [CSP, Cloning] Update DuplicateInstructionsInSplitBetween to use DomTreeUpdater.
This patch updates DuplicateInstructionsInSplitBetween to update a DTU
instead of applying updates to the DT directly.

Given that there only are 2 users, also updated them in this patch to
avoid churn.

I slightly moved the code in CallSiteSplitting around to reduce the
places where we have to pass in DTU. If necessary, I could split those
changes in a separate patch.

This fixes missing DT updates when dealing with musttail calls in
CallSiteSplitting, by using DTU->deleteBB.

Reviewers: junbuml, kuhar, NutshellySima, indutny, brzycki

Reviewed By: NutshellySima

llvm-svn: 346769
2018-11-13 17:54:43 +00:00
Steven Wu fa43892d6f Revert "[ThinLTO] Internalize readonly globals"
This reverts commit 10c84a8f35cae4a9fc421648d9608fccda3925f2.

llvm-svn: 346768
2018-11-13 17:35:04 +00:00
Louis Dionne 77c17e26ea [NFC][libcxx] Mark P1006R1 as complete
llvm-svn: 346767
2018-11-13 17:33:11 +00:00
Marshall Clow cf355fc373 Implement P0972R0: <chrono> zero(), min(), and max() should be noexcept. Reviewed as https://reviews.llvm.org/D53828
llvm-svn: 346766
2018-11-13 17:22:41 +00:00
Louis Dionne 7a83c5f623 [NFC][libcxx] Mark P1006 as implemented in LLVM 8.0
It was implemented in https://reviews.llvm.org/D53867

llvm-svn: 346765
2018-11-13 17:09:25 +00:00
Louis Dionne 7272026993 [libcxx] Implement http://wg21.link/p1006, constexpr in pointer_traits
Summary:
P1006 adds support for constexpr in the specialization of pointer_traits
for raw pointers. This is necessary in order to use pointer_traits in
the upcoming constexpr containers. We expect P1006 to be voted into the
working draft for C++20 at the San Diego meeting.

Reviewers: mclow.lists, EricWF

Subscribers: christof, dexonsmith, libcxx-commits

Differential Revision: https://reviews.llvm.org/D53867

llvm-svn: 346764
2018-11-13 17:04:05 +00:00
Louis Dionne c9c6212f6f [libcxx] GNU/Hurd uses BSD-based interfaces, but does not (and won't) provide <sys/sysctl.h>
Reviewed as https://reviews.llvm.org/D54338.

Thanks to sthibaul for the patch.

llvm-svn: 346763
2018-11-13 17:00:04 +00:00
Sanjay Patel bcc5a74261 [InstCombine] add tests for funnel shift demanded bits; NFC
llvm-svn: 346762
2018-11-13 16:47:16 +00:00
Alexander Kornienko 3635c89070 Fix uninitialized variable.
Flags variable was not initialized and later used (both isMBBSafeToOutlineFrom
implementations assume it's initialized), which breaks
test/CodeGen/AArch64/machine-outliner.mir. under memory sanitizer:
MemorySanitizer: use-of-uninitialized-value
    #0  in llvm::AArch64InstrInfo::getOutliningType(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>&, unsigned int) const llvm/lib/Target/AArch64/AArch64InstrInfo.cpp:5494:9
    #1  in (anonymous namespace)::InstructionMapper::convertToUnsignedVec(llvm::MachineBasicBlock&, llvm::TargetInstrInfo const&) llvm/lib/CodeGen/MachineOutliner.cpp:772:19
    #2  in (anonymous namespace)::MachineOutliner::populateMapper((anonymous namespace)::InstructionMapper&, llvm::Module&, llvm::MachineModuleInfo&) llvm/lib/CodeGen/MachineOutliner.cpp:1543:14
    #3  in (anonymous namespace)::MachineOutliner::runOnModule(llvm::Module&) llvm/lib/CodeGen/MachineOutliner.cpp:1645:3
    #4  in (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1744:27
    #5  in llvm::legacy::PassManagerImpl::run(llvm::Module&) llvm/lib/IR/LegacyPassManager.cpp:1857:44
    #6  in compileModule(char**, llvm::LLVMContext&) llvm/tools/llc/llc.cpp:597:8

llvm-svn: 346761
2018-11-13 16:41:05 +00:00
Simon Pilgrim e827fe09b3 [CostModel][X86] Fix constant vector XOP rights shifts
We'll constant fold these cases so they are as cheap as vector left shift cases.

Noticed while improving funnel shift costs.

llvm-svn: 346760
2018-11-13 16:40:10 +00:00
Florian Hahn 86ed347bcd [VectorUtils] Use namespace for InterleaveGroup template specialization.
llvm-svn: 346759
2018-11-13 16:26:34 +00:00
Florian Hahn a4dc7feeea [VPlan] VPlan version of InterleavedAccessInfo.
This patch turns InterleaveGroup into a template with the instruction type
being a template parameter. It also adds a VPInterleavedAccessInfo class, which
only contains a mapping from VPInstructions to their respective InterleaveGroup.
As we do not have access to scalar evolution in VPlan, we can re-use
convert InterleavedAccessInfo to VPInterleavedAccess info.


Reviewers: Ayal, mssimpso, hfinkel, dcaballe, rengolin, mkuper, hsaito

Reviewed By: rengolin

Differential Revision: https://reviews.llvm.org/D49489

llvm-svn: 346758
2018-11-13 15:58:18 +00:00
Erich Keane de6480a38c [NFC] Move storage of dispatch-version to GlobalDecl
As suggested by Richard Smith, and initially put up for review here:
https://reviews.llvm.org/D53341, this patch removes a hack that was used
to ensure that proper target-feature lists were used when emitting
cpu-dispatch (and eventually, target-clones) implementations. As a part
of this, the GlobalDecl object is proliferated to a bunch more
locations.

Originally, this was put up for review (see above) to get acceptance on
the approach, though discussion with Richard in San Diego showed he
approved of the approach taken here.  Thus, I believe this is acceptable
for Review-After-commit

Differential Revision: https://reviews.llvm.org/D53341

Change-Id: I0a0bd673340d334d93feac789d653e03d9f6b1d5
llvm-svn: 346757
2018-11-13 15:48:08 +00:00
Krasimir Georgiev 28e2dbb14d [clang-format] Do not treat the asm clobber [ as ObjCExpr
Summary:
The opening square of an inline asm clobber was being annotated as an ObjCExpr.
This caused, amongst other things, the ObjCGuesser to guess header files
containing that pattern as ObjC files.

Reviewers: benhamilton

Reviewed By: benhamilton

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D54111

llvm-svn: 346756
2018-11-13 15:38:12 +00:00
Simon Pilgrim 077a42ca9f [TTI] Make TargetTransformInfo::getOperandInfo static. NFCI.
It has no member dependencies and this makes it easier to reuse in other cost analysis code.

llvm-svn: 346755
2018-11-13 13:45:10 +00:00
Simon Pilgrim 2fe1076a08 [CostModel][X86] Add more cost tests for funnel shifts
Added full uniform/constant coverage for funnel shifts + rotates

llvm-svn: 346754
2018-11-13 12:11:15 +00:00
Simon Pilgrim 72a7fbc1a3 Fix comment for XOP rotates. NFCI.
llvm-svn: 346753
2018-11-13 12:09:27 +00:00
Simon Pilgrim 828dab341a Add bracket that was lost in rL346727 and has been causing buildbot failures for some time.
llvm-svn: 346752
2018-11-13 11:28:46 +00:00
Alexander Richardson dbfa6e616c Fix .cfi_restore with register numbers > 64
Summary:
DW_CFA_restore can only encode register numbers up to 64 (6 bits unsigned
int). For regsiter numbers > 64 we have to use DW_CFA_restore_extended
instead which uses a ULEB128 value.
I discovered this problem in the out-of-tree CHERI target since we use
DWARF register number 89 for our return capability register.

Reviewers: probinson, dblaikie, aprantl, espindola

Reviewed By: dblaikie

Subscribers: JohnReagan, emaste, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D54420

llvm-svn: 346751
2018-11-13 10:54:49 +00:00
Alexander Richardson 4eb93907f7 Fix modules build of AVRAsmParser.cpp
Summary:
Without this change I get the following error:

lib/Target/AVR/AVRGenAsmMatcher.inc:1135:1: error: redundant #include of module 'LLVM_Utils.Support.Format' appears within namespace 'llvm' [-Wmodules-import-nested-redundant]

Reviewers: dylanmckay

Reviewed By: dylanmckay

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D53425

llvm-svn: 346750
2018-11-13 10:54:44 +00:00
George Rimar 8ef9babb67 [ELF] - Renamed AArch64 specific relocations expressions. NFC.
They did not have AArch64 prefix. Now they do.

llvm-svn: 346749
2018-11-13 10:16:36 +00:00
Hans Wennborg 7717a5cd8c UserManual: Tweak the /Zc:dllexportInlines- docs some
Addressing comments on https://reviews.llvm.org/D54319

llvm-svn: 346748
2018-11-13 09:05:12 +00:00
Fangrui Song 9596848037 [ELF] .gdb_index: fix CuOff when a .debug_info section contains more than 1 DW_TAG_compile_unit
Summary:
Idx passed to readPubNamesAndTypes was an index into Chunks, not an
index into the CU list. This would be incorrect if some .debug_info
section contained more than 1 DW_TAG_compile_unit.

In real world, glibc Scrt1.o is a partial link of start.os abi-note.o init.o and contains 2 CUs in debug builds.
Without this patch, any application linking such Scrt1.o would have invalid .gdb_index
The issue could be demonstrated by:

    (gdb) py print(gdb.lookup_global_symbol('main'))
    None

Reviewers: espindola, ruiu

Reviewed By: ruiu

Subscribers: Higuoxing, grimar, dblaikie, emaste, aprantl, arichardson, JDevlieghere, arphaman, llvm-commits

Differential Revision: https://reviews.llvm.org/D54361

llvm-svn: 346747
2018-11-13 08:43:07 +00:00
Jonas Paulsson f9b2b5e67e [SystemZ] Increase the number of VLREPs
If a loaded value is replicated it is best to combine these two operations
into a VLREP (load and replicate), but isel will not produce this if the load
has other users as well.

This patch handles this by putting the other users of the load to use the
REPLICATE 0-element instead of the load. This way the load has only the
REPLICATE node as user, and we get a VLREP.

Review: Ulrich Weigand
https://reviews.llvm.org/D54264

llvm-svn: 346746
2018-11-13 08:37:09 +00:00
Craig Topper 333ab7d08b [X86] Add more tests for -x86-experimental-vector-widening-legalization
I'm looking into whether we can make this the default legalization strategy. Adding these tests to help cover the changes that will be necessary.

This patch adds copies of some tests with the command line switch enabled. By making copies its easier to compare the two legalization strategies.

I've also removed RUN lines from some of these tests that already had -x86-experimental-vector-widening-legalization

llvm-svn: 346745
2018-11-13 07:47:52 +00:00
Eric Fiselier 4de1c753ff Attempt to make benchmarks fall back to -std=c++1z when C++17 isn't supported.
The benchmarks currently require C++17, however Clang 3.9 doesn't
support -std=c++17 while still supporting all the C++17 features needed
to compile the benchmarks.

This patch makes the benchmark build attempt to fall back to -std=c++1z
when -std=c++17 isn't supported.

See llvm.org/PR39629

llvm-svn: 346744
2018-11-13 07:03:16 +00:00
Eric Fiselier 32869c6997 Add emplace tests for multiset/unordered_multiset.
This patch adds tests to ensure that multiset/unordered_multiset's emplace
method correctly constructs the elements without any intervening
constructions.

llvm-svn: 346743
2018-11-13 06:30:36 +00:00
Fedor Sergeev 8b078126a0 [FileCheck] fixing docs buildbot - use proper code-block type
llvm-svn: 346740
2018-11-13 05:47:01 +00:00
Marshall Clow d4fa0381e3 Fix PR39619 - iterator_traits isn't SFINAE-friendly enough. Thanks to Eric for the report
llvm-svn: 346738
2018-11-13 05:33:31 +00:00