202f6400ef
Function for handling byval arguments.
...
llvm-svn: 144447
2011-11-12 02:20:46 +00:00
c85e3ff334
Mips MC object code emission improvements:
...
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter
llvm-svn: 144414
2011-11-11 22:58:42 +00:00
4a63d1c0f0
Do not try to detect DAG combine patterns for integer multiply-add/sub if value
...
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.
llvm-svn: 144373
2011-11-11 04:18:21 +00:00
21cbc25bbb
64-bit atomic instructions.
...
llvm-svn: 144372
2011-11-11 04:14:30 +00:00
9189d7127f
Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.
...
llvm-svn: 144371
2011-11-11 04:11:56 +00:00
4bdfec57ba
Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.
...
llvm-svn: 144370
2011-11-11 04:06:38 +00:00
82cd9e81fc
Added invariant field to the DAG.getLoad method and changed all calls.
...
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
2011-11-08 18:42:53 +00:00
104b7e3f2c
Make changes necessary in LowerFormalArguments to support Mips64.
...
llvm-svn: 143218
2011-10-28 19:55:48 +00:00
b20a325baf
Make changes necessary in LowerCall to support Mips64.
...
llvm-svn: 143217
2011-10-28 19:49:00 +00:00
7989f15d37
Add variable IsO32 to MipsTargetLowering.
...
llvm-svn: 143213
2011-10-28 18:47:24 +00:00
4c42be5b32
Fix misc warnings. Patch by Joe Abbey.
...
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
a7e0b90897
Add definitions of conditional moves with 64-bit operands. Comment out code for
...
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed.
llvm-svn: 142226
2011-10-17 18:53:29 +00:00
09b23eb7bc
Modify lowering of GlobalAddress so that correct code is emitted when target is
...
Mips64.
llvm-svn: 141618
2011-10-11 00:55:05 +00:00
be68f3c348
Add definitions of 64-bit loads and stores. Add a patterns for unaligned
...
zextloadi32 for which there is no corresponding pseudo or real instruction.
llvm-svn: 141608
2011-10-11 00:27:28 +00:00
b1538f91dc
Add support for 64-bit divide instructions.
...
llvm-svn: 141024
2011-10-03 21:06:13 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
6a5f8b2fd4
Remove unnecessary condition check.
...
llvm-svn: 140291
2011-09-22 02:41:29 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
79738336a8
Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't
...
yet legal according to comments in LegalizeDAG.cpp:227.
Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.
The two failing tests reported in PR10876 pass after applying this patch.
llvm-svn: 140046
2011-09-19 20:26:02 +00:00
f2641e1bc1
Add codegen support for vector select (in the IR this means a select
...
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
2011-09-06 19:07:46 +00:00
7dfa791f4f
Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well enough to fix properly.
...
llvm-svn: 138751
2011-08-29 18:23:02 +00:00
419fd4f315
Fix bug in function IsShiftedMask. Remove parameter SizeInBits, which is not
...
needed for Mips32.
llvm-svn: 138132
2011-08-19 22:59:00 +00:00
fb4161ae88
Use subword loads instead of a 4-byte load when the size of a structure (or a
...
piece of it) that is being passed by value is smaller than a word.
llvm-svn: 138007
2011-08-18 23:39:37 +00:00
73d78b7ab1
Make IsShiftedMask a static function rather than defining it in an
...
anonymous namespace.
llvm-svn: 137975
2011-08-18 20:07:42 +00:00
eea541ce4e
Changed definition of EXT and INS per Bruno's comments.
...
llvm-svn: 137892
2011-08-17 22:59:46 +00:00
b2e7558c40
Add support for half-word unaligned loads and stores.
...
llvm-svn: 137848
2011-08-17 18:49:18 +00:00
184b63d09c
Move pattern matching for EXT and INS to post-legalization DAGCombine per Bruno's comment.
...
llvm-svn: 137831
2011-08-17 17:45:08 +00:00
5360f88355
Add support for ext and ins.
...
llvm-svn: 137804
2011-08-17 02:05:42 +00:00
2fcc1cfdce
Define unaligned load and store.
...
llvm-svn: 137515
2011-08-12 21:30:06 +00:00
30a49e93e3
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing.
...
I think this completes the basic CodeGen for atomicrmw and cmpxchg.
llvm-svn: 136813
2011-08-03 21:06:02 +00:00
26a484852e
Code generation for 'fence' instruction.
...
llvm-svn: 136283
2011-07-27 22:21:52 +00:00
a4c09bce9b
Lower memory barriers to sync instructions.
...
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
9663dd3f00
Change variable name.
...
llvm-svn: 135522
2011-07-19 20:56:53 +00:00
f3b29992d5
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or
...
ANDi, when the instruction does not have any immediate operands.
llvm-svn: 135520
2011-07-19 20:34:00 +00:00
0e01959327
Use descriptive variable names.
...
llvm-svn: 135514
2011-07-19 20:11:17 +00:00
db2ccdcfd2
Fix comments.
...
llvm-svn: 135496
2011-07-19 18:19:40 +00:00
e450358a21
Remove redundant instructions.
...
- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
instruction being expanded, instead of masking it in thisMBB.
- Remove redundant Or in EmitAtomicCmpSwap.
llvm-svn: 135495
2011-07-19 18:14:26 +00:00
08636b4633
Separate code that modifies control flow from code that adds instruction to
...
basic blocks.
llvm-svn: 135490
2011-07-19 17:09:53 +00:00
e4e9a590d2
Make EmitAtomic functions return the correct MachineBasicBlocks so that
...
ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.
llvm-svn: 135465
2011-07-19 03:42:13 +00:00
e97bd81f07
Do not insert instructions in reverse order.
...
llvm-svn: 135464
2011-07-19 03:14:58 +00:00
338879a7f4
Do not treat atomic.load.sub differently than other atomic binary intrinsics.
...
llvm-svn: 135418
2011-07-18 19:58:59 +00:00
27292638bd
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from
...
moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.
llvm-svn: 135415
2011-07-18 18:52:12 +00:00
8b98515c29
Change destination register operands of SC instructions so that unique
...
virtual registers are used.
llvm-svn: 135403
2011-07-18 17:44:27 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
...
llvm-svn: 135375
2011-07-18 04:54:35 +00:00
f03fa189ca
Add an intrinsic and codegen support for fused multiply-accumulate. The intent
...
is to use this for architectures that have a native FMA instruction.
llvm-svn: 134742
2011-07-08 21:39:21 +00:00
9c6028f98e
Lower MachineInstr to MC Inst and print to .s files.
...
llvm-svn: 134661
2011-07-07 23:56:50 +00:00
2e766ed2f8
Reverse order of operands of address operand mem so that the base operand comes
...
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
2011-07-07 18:57:00 +00:00
eaf77dc2bd
Update comment for getRegForInlineAsmConstraint for Mips.
...
llvm-svn: 134087
2011-06-29 19:33:04 +00:00
9519c08a43
Remove getRegClassForInlineAsmConstraint for Mips.
...
Part of rdar://9643582
llvm-svn: 134084
2011-06-29 19:04:31 +00:00
35792089e7
Change the chain input of nodes that load the address of a function. This change
...
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.
llvm-svn: 133811
2011-06-24 19:01:25 +00:00
5b350be79d
Coding style fixes.
...
llvm-svn: 133496
2011-06-21 01:02:03 +00:00
4c406e7457
Re-apply 132758 and 132768 which were speculatively reverted in 132777.
...
llvm-svn: 133494
2011-06-21 00:40:49 +00:00
5444a7b4cd
Silence warnings in non assert builds. Patch by David Blaikie
...
llvm-svn: 133118
2011-06-16 00:40:02 +00:00
f15601f19a
Speculatively revert 132758 and 132768 to try to fix the Windows buildbots.
...
llvm-svn: 132777
2011-06-09 16:03:19 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
...
No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
4e9af454f7
Fix bug in lowering of DYNAMIC_STACKALLOC nodes. The correct offset of the
...
dynamically allocated stack area was not set.
llvm-svn: 132758
2011-06-08 21:28:09 +00:00
195a1e2184
Reorganize code in MipsTargetLowering::LowerCall to improve readability.
...
llvm-svn: 132756
2011-06-08 17:39:33 +00:00
41956cf6e3
Refactor MipsTargetLowering::EmitInstrWithCustomInserter.
...
llvm-svn: 132726
2011-06-07 19:28:39 +00:00
1550678765
Coding style fixes.
...
- Fix indentation.
- Move comments.
- Fit lines in 80 columns.
- Remove dead code.
llvm-svn: 132724
2011-06-07 18:58:42 +00:00
6627752050
Custom-lower FRAMEADDR. Patch by Sasa Stankovic.
...
llvm-svn: 132444
2011-06-02 00:24:44 +00:00
f771a0f490
Fix uninitialized variables and silence warnings
...
llvm-svn: 132355
2011-05-31 20:25:26 +00:00
98fc4c8bbc
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,
...
nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.
Patch by Sasa Stankovic.
llvm-svn: 132323
2011-05-31 02:54:07 +00:00
bf3c1251e0
This patch implements the thread local storage. Implemented are General
...
Dynamic, Initial Exec and Local Exec TLS models.
Patch by Sasa Stankovic
llvm-svn: 132322
2011-05-31 02:53:58 +00:00
b406843fe5
Define a wrapper node for target constant nodes (tglobaladdr, etc.).
...
Need this to prevent emitting illegal conditional move instructions.
llvm-svn: 132240
2011-05-28 01:07:07 +00:00
077964a03c
Use MachineFrameInfo::hasCalls instead of MipsFunctionInfo::hasCall to check if
...
a function has any function calls.
llvm-svn: 132140
2011-05-26 20:30:31 +00:00
aa560006ed
Add support for C++ exception handling.
...
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
f1412e4d2f
Remove MipsTargetLowering::LowerFP_TO_SINT. Patterns for fp_to_sint have already
...
been defined in MipsInstrFPU.td.
llvm-svn: 132076
2011-05-25 20:08:05 +00:00
44eba3ac49
Custom-lower FCOPYSIGN nodes.
...
llvm-svn: 132074
2011-05-25 19:32:07 +00:00
d72cc55fcc
Update MaxCallFrameSize regardless of the relocation model selected.
...
llvm-svn: 132070
2011-05-25 18:08:32 +00:00
92a26d4e18
Change initial value of MaxCallFrameSize. MipsFI::getMaxCallFrameSize() should
...
return 0 if there are no function calls made.
llvm-svn: 132065
2011-05-25 17:52:48 +00:00
46662e0f91
Coding style fixes. Added comments.
...
llvm-svn: 132063
2011-05-25 17:32:06 +00:00
aac670c1c8
Fix lowering of DYNAMIC_STACKALLOC nodes.
...
llvm-svn: 132030
2011-05-25 02:20:00 +00:00
5e16c6a9b2
Implement byval structure argument passing. The following limitations or
...
deficiencies exist:
- Works only if ABI is o32.
- Zero-sized structures cannot be passed.
- There is a lot of redundancy in generated code.
llvm-svn: 131986
2011-05-24 19:18:33 +00:00
cb4a1a8d3f
Simplify offset calculation of stack frame objects for $gp restore location and
...
variable arguments in LowerCall and LowerFormalArguments. This should also fix
the bug in which handling of variable arguments is incorrect when the front-end
optimizes away unused fixed arguments.
llvm-svn: 131942
2011-05-24 00:23:52 +00:00
dfb8cda11f
Expand f64 FPOW.
...
llvm-svn: 131928
2011-05-23 22:23:58 +00:00
9dbb45b596
Fixes related to coding style.
...
llvm-svn: 131922
2011-05-23 21:13:59 +00:00
f9e5750fc8
Change StackDirection from StackGrowsUp to StackGrowsDown.
...
The following improvements are accomplished as a result of applying this patch:
- Fixed frame objects' offsets (relative to either the virtual frame pointer or
the stack pointer) are set before instruction selection is completed. There is
no need to wait until Prologue/Epilogue Insertion is run to set them.
- Calculation of final offsets of fixed frame objects is straightforward. It is
no longer necessary to assign negative offsets to fixed objects for incoming
arguments in order to distinguish them from the others.
- Since a fixed object has its relative offset set during instruction
selection, there is no need to conservatively set its alignment to 4.
- It is no longer necessary to reorder non-fixed frame objects in
MipsFrameLowering::adjustMipsStackFrame.
llvm-svn: 131915
2011-05-23 20:16:59 +00:00
0837692ac6
Change the order fixed objects are created in MipsTargetLowering::LowerCall in
...
preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
llvm-svn: 131767
2011-05-20 23:22:14 +00:00
7c619f174a
In CC_MipsO32, allocate a stack space regardless of whether the argument is
...
passed in register or on the stack.
llvm-svn: 131758
2011-05-20 21:39:54 +00:00
43407fe633
Make $fp and $ra callee-saved registers and let PrologEpilogInserter handle
...
saving and restoring them.
llvm-svn: 131745
2011-05-20 18:39:33 +00:00
fe4f9d5977
Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic
...
llvm-svn: 131714
2011-05-20 02:30:51 +00:00
7489faa0c1
Remove code that creates unnecessary frame objects.
...
llvm-svn: 131711
2011-05-20 01:45:06 +00:00
9e6a8cca5d
Align i64 arguments to 64 bit boundaries.
...
llvm-svn: 131668
2011-05-19 20:29:48 +00:00
92ab6db6c8
Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic.
...
llvm-svn: 131657
2011-05-19 18:06:05 +00:00
2518f8376d
Make the logic for determining function alignment more explicit. No functionality change.
...
llvm-svn: 131012
2011-05-06 20:34:06 +00:00
23e8ecf125
Prevent instructions using $gp from being placed between a jalr and the instruction that restores the clobbered $gp.
...
llvm-svn: 130847
2011-05-04 17:54:27 +00:00
0e7ee666b7
Lower BlockAddress node when relocation-model is static.
...
llvm-svn: 130131
2011-04-25 17:10:45 +00:00
e24891251c
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
...
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
aef55c8801
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
...
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
279169771b
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
...
llvm-svn: 129594
2011-04-15 19:52:08 +00:00
0ab5e2cded
Fix a ton of comment typos found by codespell. Patch by
...
Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
d6f1c58914
Fix handling of functions with internal linkage.
...
llvm-svn: 129099
2011-04-07 19:51:44 +00:00
5ec2ead9b0
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.
...
llvm-svn: 128830
2011-04-04 17:11:07 +00:00
4111db6575
Undo changes mistakenly made in revision 128750.
...
llvm-svn: 128751
2011-04-02 00:26:12 +00:00
977f555a76
Insert space before ';' to prevent warnings.
...
llvm-svn: 128750
2011-04-02 00:15:58 +00:00
56d9ef53a2
Simplifies logic for printing target flags.
...
llvm-svn: 128741
2011-04-01 21:41:06 +00:00
a535270d91
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
...
llvm-svn: 128650
2011-03-31 18:26:17 +00:00
4e9ca1b3ba
fixed typo
...
llvm-svn: 128574
2011-03-30 21:15:35 +00:00
05a23b1e61
silence a conditional assignment -Wuninitialized warning.
...
llvm-svn: 127453
2011-03-11 02:12:51 +00:00
048ffabe78
Improve varags handling, with testcases. Patch by Sasa Stankovic
...
llvm-svn: 127349
2011-03-09 19:22:22 +00:00
434248a62c
Improve div/rem node handling on mips. Patch by Akira Hatanaka
...
llvm-svn: 127034
2011-03-04 21:03:24 +00:00
8887d6593f
Rewrite and simplify o32 vaarg passing, no functional changes. Patch by Sasa Stankovic
...
llvm-svn: 127029
2011-03-04 20:27:44 +00:00
f8198e4311
Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka
...
llvm-svn: 127027
2011-03-04 20:01:52 +00:00
22b69db8dd
Expands FCOS and FSIN nodes when type is f64.
...
llvm-svn: 127017
2011-03-04 18:54:14 +00:00
61a61e9da3
Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka with some small modifications by me.
...
llvm-svn: 125292
2011-02-10 18:05:10 +00:00
b02a9dfa55
Negative zero is not legal on mips. Patch by Sasa Stankovic
...
llvm-svn: 123766
2011-01-18 19:41:41 +00:00
ac517fa9f7
Handle (i32,i32) => f64 in a cleaner way. Patch by Sasa Stankovic
...
llvm-svn: 123763
2011-01-18 19:38:25 +00:00
4dc73fa075
Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka
...
llvm-svn: 123760
2011-01-18 19:29:17 +00:00
3e5fbd74ed
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
...
something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
2010-12-21 02:38:05 +00:00
d47180e45e
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
...
llvm-svn: 121377
2010-12-09 17:32:30 +00:00
b9bfd0945a
Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again
...
llvm-svn: 121164
2010-12-07 19:04:14 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
...
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
802527adad
eliminate some uses of the getStore overload.
...
llvm-svn: 114453
2010-09-21 17:50:43 +00:00
7727d05dbb
convert the targets off the non-MachinePointerInfo of getLoad.
...
llvm-svn: 114410
2010-09-21 06:44:06 +00:00
160695fecb
Fix PR7174, a couple o Mips fixes:
...
- Fix a typo for PIC check during jmp table lowering
- Also fix the "first jump table basic block is not
considered only reachable by fall through" problem, use this
ad-hoc solution until I come up with something better.
Patch by stetorvs@gmail.com
llvm-svn: 108820
2010-07-20 08:37:04 +00:00
ea7863647b
Fix Mips PR7473. Patch by stetorvs@gmail.com
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llvm-svn: 108816
2010-07-20 07:58:51 +00:00
fe7532a308
Split the SDValue out of OutputArg so that SelectionDAG-independent
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code can do calling-convention queries. This obviates OutputArgReg.
llvm-svn: 107786
2010-07-07 15:54:55 +00:00
a3ca21b228
Propagate debug loc.
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llvm-svn: 107710
2010-07-06 22:08:15 +00:00
3439629239
Reapply r107655 with fixes; insert the pseudo instruction into
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the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.
llvm-svn: 107691
2010-07-06 20:24:04 +00:00
f4f04107ef
Revert r107655.
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llvm-svn: 107668
2010-07-06 15:49:48 +00:00
12205645a6
Fix a bunch of custom-inserter functions to handle the case where
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the pseudo instruction is not at the end of the block.
llvm-svn: 107655
2010-07-06 15:18:19 +00:00
0664a67fe1
Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.
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llvm-svn: 107550
2010-07-03 00:40:23 +00:00
25c1653700
Get rid of the EdgeMapping map. Instead, just check for BasicBlock
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changes before doing phi lowering for switches.
llvm-svn: 102809
2010-05-01 00:01:06 +00:00
21cea8ac2e
Use const qualifiers with TargetLowering. This eliminates several
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const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
2010-04-17 15:26:15 +00:00
31ae586c74
Move per-function state out of TargetLowering subclasses and into
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MachineFunctionInfo subclasses.
llvm-svn: 101634
2010-04-17 14:41:14 +00:00
bcaf681cde
Add const qualifiers to CodeGen's use of LLVM IR constructs.
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llvm-svn: 101334
2010-04-15 01:51:59 +00:00
3cd87cc5ee
Remove an assumption of default arguments. This is in anticipation of a
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change to SelectionDAG build APIs.
llvm-svn: 96233
2010-02-15 16:56:10 +00:00
d59cddc098
Add suport for VASTART on Mips.
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llvm-svn: 95506
2010-02-06 21:00:02 +00:00
d6fff557db
First step towards varargs support in Mips:
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- o32 cc must pass all arguments in A0...A3 and stack regardless
if its type (but respect the alignment).
- Store all variable arguments back to the caller stack.
llvm-svn: 95500
2010-02-06 19:20:49 +00:00
6f36a083ef
Revert 95130.
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llvm-svn: 95160
2010-02-02 23:55:14 +00:00
c1b0116ff1
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
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llvm-svn: 95130
2010-02-02 21:29:10 +00:00
193e64c699
Fix PR6144. Reload GP before the emission of CALLSEQ_END to guarantee the right reload order
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llvm-svn: 94915
2010-01-30 18:32:07 +00:00
67a69dd2ed
Eliminate target hook IsEligibleForTailCallOptimization.
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Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
llvm-svn: 94626
2010-01-27 00:07:07 +00:00
547c761dd6
eliminate the TargetLowering::UsesGlobalOffsetTable bool, which is
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subsumed by TargetLowering::getJumpTableEncoding(). Change uses of
it to be more specific.
llvm-svn: 94529
2010-01-26 06:53:37 +00:00
2db07581b7
Support PIC loading of constant pool entries
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llvm-svn: 89863
2009-11-25 12:17:58 +00:00
de5dea869f
Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
llvm-svn: 89711
2009-11-23 23:20:51 +00:00
ed85e12da6
We are not using DBG_STOPPOINT anymore.
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llvm-svn: 89536
2009-11-21 02:46:55 +00:00
537e409c58
- Fix a small bug while handling target constant pools (one param was missing).
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- Add a smarter constant pool loading, instead of:
lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)
Generate:
lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)
llvm-svn: 88886
2009-11-16 04:33:42 +00:00
1fbe054450
Add a bool flag to StackObjects telling whether they reference spill
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slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
llvm-svn: 87022
2009-11-12 20:49:22 +00:00
83896a59e1
Add a second ValueType argument to isFPImmLegal.
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llvm-svn: 85361
2009-10-28 01:43:28 +00:00
16993aa30b
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.
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llvm-svn: 85281
2009-10-27 19:56:55 +00:00
Akira Hatanaka