Commit Graph

49 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen b659c76c77 Fix PR6283.
When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072
2010-02-13 02:06:10 +00:00
Chris Lattner ea26fa9971 fix a layering violation: VirtRegRewriter.cpp shouldn't use AsmPrinter.h.
llvm-svn: 95748
2010-02-10 01:23:18 +00:00
Chris Lattner c9505b68c8 fix missing #includes.
llvm-svn: 95745
2010-02-10 01:17:36 +00:00
Chris Lattner b06015aa69 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Jakob Stoklund Olesen 7725526de1 Add <imp-def> and <imp-kill> operands when replacing virtual sub-register defs and kills.
An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812
2010-01-06 00:29:28 +00:00
David Greene e3f851db18 Change errs() to dbgs().
llvm-svn: 92590
2010-01-05 01:25:52 +00:00
Chris Lattner a48f44d9ee improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!

llvm-svn: 90365
2009-12-03 00:50:42 +00:00
Jakob Stoklund Olesen 2bbeaa8774 Add MachineBasicBlock::getName, and use it in place of getBasicBlock()->getName.
Fix debug code that assumes getBasicBlock never returns NULL.

llvm-svn: 89428
2009-11-20 01:17:03 +00:00
Lang Hames e9e0cd4e27 Fixed the in-place spiller and trivial rewriter, which had been broken by the recent SlotIndexes work.
llvm-svn: 89238
2009-11-18 20:31:20 +00:00
Evan Cheng 16797a1f55 Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter.
llvm-svn: 88753
2009-11-14 03:42:17 +00:00
Evan Cheng 6ad7da96fe - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
2009-11-14 02:55:43 +00:00
Evan Cheng d2c10508cd Fix PR5412: Fix an inverted check and another missing sub-register check.
llvm-svn: 88738
2009-11-14 02:09:09 +00:00
Evan Cheng 78fa302e7d Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.
llvm-svn: 88719
2009-11-13 23:16:41 +00:00
David Greene 7cf326aed4 Set the ReloadReuse AsmPrinter flag where appropriate.
llvm-svn: 87030
2009-11-12 21:07:54 +00:00
Dale Johannesen 8829fc3a18 When there is a 2-instruction spill sequence, record
the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

llvm-svn: 85463
2009-10-29 01:15:40 +00:00
Dale Johannesen 14f162d9dc When we generate spill code, then decide we don't need
to spill after all, we weren't handling 2-instruction
spill sequences correctly (PPC Altivec).  We need to
remove the store in this case.  Removing the other
instruction(s) would be goodness but is not needed for
correctness, and isn't done here.  7331562.

llvm-svn: 85437
2009-10-28 21:56:18 +00:00
Evan Cheng b81cb2a9a8 - Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.

llvm-svn: 85091
2009-10-26 04:56:07 +00:00
Evan Cheng 4c799e65d7 Use isIdentityCopy. Fix a bozo bug (flipped condition) in InvalidateRegDef.
llvm-svn: 85047
2009-10-25 07:51:47 +00:00
Nick Lewycky 974e12b2d3 Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.

llvm-svn: 85043
2009-10-25 06:57:41 +00:00
Nick Lewycky 02d5f77d26 Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042
2009-10-25 06:33:48 +00:00
Dale Johannesen 06243d7bf2 Revert the kludge in 76703. I got a clean
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.

llvm-svn: 83871
2009-10-12 18:49:00 +00:00
Duncan Sands 2fbeaf084f Remove some unused variables and methods warned about by
icc (#177, partial).  Patch by Erick Tryzelaar.

llvm-svn: 81106
2009-09-06 08:33:48 +00:00
Lang Hames 0b3720b3c3 Fixed a test that ensures the LocalRewriter does not attempt to
avoid reloads by reusing clobbered registers.

This was causing issues in 256.bzip2 when compiled with PIC for
a while (starting at r78217), though the problem has since been masked. 

llvm-svn: 80872
2009-09-03 02:52:02 +00:00
Jakob Stoklund Olesen 972c8fab51 Fix PR4753.
When undoing a reuse in ReuseInfo::GetRegForReload, check if it was only a
sub-register being used. The MachineOperand::getSubReg() method is only valid
for virtual registers, so we have to recover the sub-register index manually.

llvm-svn: 79855
2009-08-23 13:01:45 +00:00
Benjamin Kramer 1a25d733f9 Kill off more cerr/cout uses and prune includes a bit.
llvm-svn: 79852
2009-08-23 11:37:21 +00:00
Chris Lattner ed03a01af1 remove some DOUTs
llvm-svn: 79812
2009-08-23 03:20:44 +00:00
Jakob Stoklund Olesen abff8fcb1c Update LocalRewriter::DistanceMap when inserting stack loads.
In the included test case, a stack load was not included in DistanceMap. That
caused TransferDeadness to ignore the instruction, leading to a scavenger
assert.

llvm-svn: 79090
2009-08-15 11:03:03 +00:00
Dan Gohman a6d0afcb74 Fix a bunch of namespace pollution.
llvm-svn: 78363
2009-08-07 01:32:21 +00:00
David Greene 71ab2fdddd Add reload and remat backscheduling. This is disabled by default. Use
-schedule-spills=true to enable.

llvm-svn: 77327
2009-07-28 16:49:24 +00:00
Daniel Dunbar 0dd5e1ed39 More migration to raw_ostream, the water has dried up around the iostream hole.
- Some clients which used DOUT have moved to DEBUG. We are deprecating the
   "magic" DOUT behavior which avoided calling printing functions when the
   statement was disabled. In addition to being unnecessary magic, it had the
   downside of leaving code in -Asserts builds, and of hiding potentially
   unnecessary computations.

llvm-svn: 77019
2009-07-25 00:23:56 +00:00
Evan Cheng 4dc848f3e8 Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.

llvm-svn: 76703
2009-07-22 00:25:27 +00:00
Evan Cheng 07a6ac6b29 Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.
llvm-svn: 76558
2009-07-21 09:15:00 +00:00
Evan Cheng e20cbf3068 Enable cross register class coalescing.
llvm-svn: 76281
2009-07-18 02:10:10 +00:00
Evan Cheng 76b561dd70 Fix my brain cramp by inverting the assertion condition.
llvm-svn: 76131
2009-07-17 00:32:06 +00:00
Daniel Dunbar f60abdbb5a Disable this assert for now, it is firing on an llvm-gcc bootstrap. :(
llvm-svn: 76123
2009-07-16 23:02:46 +00:00
Daniel Dunbar 87b85dd4dc Fix inverted preprocessor conditional.
llvm-svn: 76111
2009-07-16 22:08:25 +00:00
Evan Cheng 357645efad Changed my mind. We now allow remat of instructions whose defs have subreg indices.
llvm-svn: 76100
2009-07-16 20:15:00 +00:00
Evan Cheng 84517443ca Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900
2009-07-16 09:20:10 +00:00
Torok Edwin fbcc663cbf llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").

llvm-svn: 75640
2009-07-14 16:55:14 +00:00
Torok Edwin 56d0659726 assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.

llvm-svn: 75379
2009-07-11 20:10:48 +00:00
Evan Cheng f075943584 Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.
llvm-svn: 75264
2009-07-10 19:15:51 +00:00
Evan Cheng d379e896ff Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
llvm-svn: 74580
2009-07-01 01:59:31 +00:00
Evan Cheng 0dc101b897 Add a bit IsUndef to MachineOperand. This indicates the def / use register operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them.
The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing.

This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def.

llvm-svn: 74518
2009-06-30 08:49:04 +00:00
Lang Hames 1a65f61137 Removed SimpleRewriter.
llvm-svn: 72880
2009-06-04 18:45:36 +00:00
Evan Cheng b39a6be77a Fix for PR4225: When rewriter reuse a value in a physical register , it clear the register kill operand marker and its kill ops information. However, the cleared operand may be a def of a super-register. Clear the kill ops info for the super-register's sub-registers as well.
llvm-svn: 72758
2009-06-03 09:00:27 +00:00
Lang Hames fc968ef687 Update to in-place spilling framework. Includes live interval scaling and trivial rewriter.
llvm-svn: 72729
2009-06-02 16:53:25 +00:00
Evan Cheng e23c109a67 Fix PR4210. Rewritter should track and update kills of sub-registers as well.
llvm-svn: 71848
2009-05-15 06:48:19 +00:00
Evan Cheng df1aeeeb90 Teach TransferDeadness to delete truly dead instructions if they do not produce side effects.
llvm-svn: 71606
2009-05-12 23:07:00 +00:00
Lang Hames ab68cf24bb Renamed Spiller classes (plus uses and related files) to VirtRegRewriter.
llvm-svn: 71057
2009-05-06 02:36:21 +00:00