Commit Graph

20 Commits

Author SHA1 Message Date
Alp Toker cb40291100 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Andrew Trick 40c4f38071 Support BufferSize on ProcResGroup for unified MOp schedulers.
And add Sandybridge/Haswell resource buffers.

llvm-svn: 184034
2013-06-15 04:50:06 +00:00
Andrew Trick cf398b220d Machine model: verify well-formed processor resource groups.
llvm-svn: 180161
2013-04-23 23:45:14 +00:00
Andrew Trick bf8a28dc52 Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

llvm-svn: 177226
2013-03-16 18:58:55 +00:00
Richard Smith a7bb16ad86 Fix an uninitialized member variable, found by -fsanitize=bool.
llvm-svn: 170627
2012-12-20 01:05:39 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/...
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
2012-12-04 10:37:14 +00:00
Andrew Trick d0b9c44583 TableGen subtarget emitter cleanup.
Consistently evaluate Aliases and Sequences recursively.

llvm-svn: 165604
2012-10-10 05:43:13 +00:00
Andrew Trick 9e1deb69b9 Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.

llvm-svn: 165180
2012-10-03 23:06:32 +00:00
Andrew Trick da984b1aa9 TableGen subtarget emitter, nearly first class support for SchedAlias.
A processor can now arbitrarily alias one SchedWrite onto
another. Only the SchedAlias definition need be within the processor
model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or
transitively refer to another alias.

llvm-svn: 165179
2012-10-03 23:06:28 +00:00
Andrew Trick 9257b8f8bb Machine Model (-schedmodel only). Added SchedAliases.
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

llvm-svn: 164451
2012-09-22 02:24:21 +00:00
Andrew Trick cfe222c2a9 SchedMachineModel: compress the CPU's WriteLatencyTable.
llvm-svn: 164199
2012-09-19 04:43:19 +00:00
Andrew Trick ea28dbdf93 comment typo
llvm-svn: 164097
2012-09-18 04:03:30 +00:00
Andrew Trick a88f1bddc6 TableGen subtarget emitter. Use getSchedClassIdx.
llvm-svn: 164096
2012-09-18 03:55:55 +00:00
Andrew Trick 8e7f202e32 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
2012-09-17 23:00:42 +00:00
Andrew Trick c00f4314ce comment typo
llvm-svn: 164064
2012-09-17 22:19:04 +00:00
Andrew Trick 36e07eb83e TableGen subtarget emitter. Use getSchedClassIdx.
llvm-svn: 164063
2012-09-17 22:19:01 +00:00
Andrew Trick 1e46d48814 TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs.

llvm-svn: 163953
2012-09-15 00:20:02 +00:00
Andrew Trick 33401e8469 TableGen subtarget parser. Handle new machine model.
Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952
2012-09-15 00:19:59 +00:00
Andrew Trick 766864963b TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
2012-09-15 00:19:57 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00