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Author SHA1 Message Date
Artem Tamazov 54bfd548aa [AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions. 
Fixes Bug 30808.
Note that passing subtarget information to predicates seems too complicated, so gfx8-specific def smrd_offset_20 introduced.
Old gfx6/7-specific def renamed to smrd_offset_8 for clarity.
Lit tests updated.

Differential Revision: https://reviews.llvm.org/D26085

llvm-svn: 285590
 2016-10-31 16:07:39 +00:00
Valery Pykhtin c4546ec0cf [AMDGPU] add VI disassembler tests. NFC. 
Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon).

Differential Revision: http://reviews.llvm.org/D18249

llvm-svn: 263729
 2016-03-17 17:56:33 +00:00
Valery Pykhtin a4db224d54 [AMDGPU] Fix SMEM instructions encoding/operand namings 
Differential Revision: http://reviews.llvm.org/D17651

llvm-svn: 263108
 2016-03-10 13:06:08 +00:00