5 Commits

Author	SHA1	Message	Date
David Green	32556a9832	[ARM] Remove more unused check prefixes, NFC	2020-11-14 15:37:53 +00:00
Simon Pilgrim	7d766c393e	[ARM] Regenerate BSWAP16 tests ... llvm-svn: 367543	2019-08-01 11:12:10 +00:00
David Blaikie	a79ac14fa6	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction ... Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794	2015-02-27 21:17:42 +00:00
Louis Gerbarg	b4013235e3	Fix ARM bswap16.ll test on Windows ... Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. llvm-svn: 208638	2014-05-12 22:13:07 +00:00
Louis Gerbarg	efdcf23736	Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb ... The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620	2014-05-12 19:53:52 +00:00