Commit Graph

345727 Commits

Author SHA1 Message Date
Fred Riss acd641c19d [lldb/testsuite] Slightly rework TestHiddenIvars.py
The test was stripping the binaries from the Python
code. Unfortunately, if running on darwin embedded in a context that
requires code signing, the stripping was invalidating the signature,
thus breaking the test.

This patch moves the stripping to the Makefile and resigns the
stripped binaries if required.
2020-03-18 20:52:28 -07:00
Fred Riss 71db787c45 [lldb/testsuite] Rewrite TestThreadLocal.py
It was an inline test before. Clang stopped emitting line information
for the TLS initialization and the inline test didn't have a way to
break before it anymore.

This rewrites the test as a full-fldeged python test and improves the
checking of the error case to verify that the failure we are looking
for is related to the TLS setup not being complete.
2020-03-18 20:52:28 -07:00
Fred Riss 127b9d9d77 [lldb/testsuite] Apply @skipIfDarwinEmbedded to part of TestHWBreakMultiThread
The comment in the test wrongfully claimed that we support hardware
breakpoints on darwin for arm64, but we never did.
2020-03-18 20:52:28 -07:00
Fred Riss c182be211a [lldb/testsuite] Tweak TestBreakpointLocations.py to pass for arm64
The test checks that we correctly set the right number of breakpoints
when breaking into an `always_inline` function. The line of this
funstion selected for this test was the return statement, but with
recent compiler, this return statement doesn't necessarily exist after
inlining, even at O0.

Switch the breakpoint to a different line of the inline function.
2020-03-18 20:52:28 -07:00
Fred Riss 52b2bae777 [lldb/testsuite] Skip TestEmptyStdModule.py if using a remote platform
The test runs `platform select host`, so it make no sense to run it
when remote debugging.
2020-03-18 20:52:28 -07:00
Chen Zheng aacf022cd5 [PowerPC] add IR level isFMAFasterThanFMulAndFAdd - NFC
And also refactor legacy MIR level isFMAFasterThanFMulAndFAdd.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D76265
2020-03-18 23:24:40 -04:00
Rob Suderman cd1212deff [mlir] Introduced CallOp Dialect Conversion
Summary:
Utility to perform CallOp Dialect conversion, specifically handling cases where
an argument type has changed and the corresponding CallOp needs to be updated.

Differential Revision: https://reviews.llvm.org/D76326
2020-03-18 20:07:38 -07:00
Geoffrey Martin-Noble b72e13c242 [MLIR] Deduplicate dialect registration by ClassID
Summary:
With the move towards dialect registration that does not depend only use
static initialization, we are running into more cases where the dialects
are registered by different methods. For example, TensorFlow still uses
static initialization to register all MLIR core dialects, which prevents
explicit registration of any of them when linking it in. We ran into this
issue in https://github.com/google/iree/pull/982.

To address potential issues with conflicts from non-standard
allocators passed to registerDialectAllocator, made this method
private. Now all dialects can only be registered with their
constructor.

Similarly deduplicates DialectHooks for consistency and makes their
registration follow the same pattern.

Differential Revision: https://reviews.llvm.org/D76329
2020-03-18 19:52:27 -07:00
Davide Italiano f0ca0a2538 [AppleObjCRuntimeV2] Rewrite GetClassDescriptor, reducing indentation.
I'm going to modify this function to account for lazily allocated
class names in the Obj-C runtime, but first I need to understand
what it does.
2020-03-18 19:23:58 -07:00
Yaxun (Sam) Liu 62201763c5 Fix crash in check-mlir due to 08ab8c9af4 2020-03-18 21:50:00 -04:00
Lei Zhang 73431a492b [mlir][spirv] Consolidate std.constant to spv.constant conversions
This commit merges the DRR pattern for std.constant to spv.constant
conversion into the C++ OpConversionPattern. This allows us to have
remove the DRR pattern file. Along the way, this commit enhanced
std.constant to spv.constant conversion to consider type conversions,
which means converting the underlying attributes if necessary.

Differential Revision: https://reviews.llvm.org/D76246
2020-03-18 20:11:05 -04:00
Lei Zhang ffd4583c6a [mlir][spirv] Change standard op patterns to consider type conversion
Previously we have a few patterns that were written with DRR. DRR
at the moment does not work nicely with dialect conversion framework.
It generates normal RewritePatterns, while the dialect conversion
framework requires ConversionPatterns to take into consideration
the type conversion. So this commit starts to change existing DRR
patterns for standard ops to OpConversionPattern to incorporate the
SPIR-V type conversion. All patterns are converted except the one
for constant ops, which will happen in a subsequent commit.

Differential Revision: https://reviews.llvm.org/D76245
2020-03-18 20:11:05 -04:00
Lei Zhang 9efb4b4023 [mlir][spirv] Make SPIRVTypeConverter target environment aware
Non-32-bit scalar types requires special hardware support that may
not exist on all Vulkan-capable GPUs. This is reflected as non-32-bit
scalar types require special capabilities or extensions to be used.
This commit makes SPIRVTypeConverter target environment aware so
that it can properly convert standard types to what is accepted on
the target environment.

Right now if a scalar type bitwidth is not supported in the target
environment, we use 32-bit unconditionally. This requires Vulkan
runtime to also feed in data with a matched bitwidth and layout,
especially for interface types. The Vulkan runtime can do that by
inspecting the SPIR-V module. Longer term, we might want to introduce
a way to control how such case are handled and explicitly fail
if wanted.

Differential Revision: https://reviews.llvm.org/D76244
2020-03-18 20:11:05 -04:00
Lei Zhang f741b8eabe [mlir][spirv] Move type checks from dialect class to type hierarchy
Types should be checked with the type hierarchy. This should result in
better responsibility division and API surface.

Differential Revision: https://reviews.llvm.org/D76243
2020-03-18 20:11:05 -04:00
Lei Zhang 58df5e6d9a [mlir][spirv] Plumbing target environment into type converter
This commit unifies target environment queries into a new wrapper
class spirv::TargetEnv and shares across various places needing
the functionality. We still create multiple instances of TargetEnv
though given the parent components (type converters, passes,
conversion targets) have different lifetimes.

In the meantime, LowerABIAttributesPass is updated to take into
consideration the target environment, which requires updates to
tests to provide that.

Differential Revision: https://reviews.llvm.org/D76242
2020-03-18 20:11:05 -04:00
Lei Zhang 67e8690e53 [mlir][spirv] Let SPIRVConversionTarget consider type availability
Previously we only consider the version/extension/capability requirement
on the op itself. This commit updates SPIRVConversionTarget to also
take into consideration the values' types when deciding op legality.

Differential Revision: https://reviews.llvm.org/D75876
2020-03-18 20:11:04 -04:00
Lei Zhang 3b35f9d8b5 [mlir][spirv] Use memref memory space for storage class
Previously in SPIRVTypeConverter, we always convert memref types
to StorageBuffer regardless of their memory spaces. This commit
fixes that to let the conversion to look into memory space
properly. For this purpose, a mapping between SPIR-V storage class
and memref memory space is introduced. The mapping is arbitary
decided at the moment and the hope is that we can leverage
string memory space later to be more clear.

Now spv.interface_var_abi cannot contain storage class unless it's
attached to a scalar value, where we need the storage class as side
channel information. Verifications and tests are properly adjusted.

Differential Revision: https://reviews.llvm.org/D76241
2020-03-18 20:11:04 -04:00
Craig Topper c69a4d6bef [SelectionDAG] When splitting gathers/scatters in type legalization, set MMO size to UnknownSize
Gather/scatter don't access one memory location, they access multiple disjoint locations. So using a fixed size isn't accurate. But we don't have a way to represent the true behavior so just use UnknownSize.

Previously we "split" the memory VT and use that size for the MMO of each half. But the memory VT is scalar so splitting usually just returned the original scalar VT, but on 32-bit X86 if the scalar VT was i64 it probably returned i32?

Differential Revision: https://reviews.llvm.org/D76388
2020-03-18 16:07:15 -07:00
Sanjay Patel d8061456bc [LangRef] fix typo in select poison explanation; NFC 2020-03-18 18:59:14 -04:00
Richard Smith f18233dad4 Fix -fsanitize=array-bound to treat T[0] union members as flexible array
members regardless of whether they're the last member of the union.
2020-03-18 15:47:24 -07:00
Vedant Kumar 47622efc6f [clang/test] Add test for DIFlagAllCallsDescribed under -ggdb + -gdwarf-4, NFC 2020-03-18 15:24:13 -07:00
Nathan James 1365ab4b63 [clang-tidy] RenamerClangTidy now correctly renames `using namespace` decls
Summary: Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=45039 | readability-identifier-naming doesn't rename using namespace correctly. ]]

Reviewers: aaron.ballman, gribozavr2, JonasToth, hokein, alexfh

Reviewed By: aaron.ballman

Subscribers: xazax.hun, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75220
2020-03-18 22:14:40 +00:00
Jonas Devlieghere 5ffb30fd6c [lldb/PlatformDarwin] Expose current toolchain and CL tools directory
Expose two methods to find the current toolchain and the current command
line tools directory. These are used by Swift to find the resource
directory.
2020-03-18 15:08:24 -07:00
Jonas Devlieghere 14970669dd [lldb/Test] Add unittest for FileSpec::operator bool() 2020-03-18 15:08:23 -07:00
Louis Dionne f951b0f82d [lit] Add builtin support for flaky tests in lit
This commit adds a new keyword in lit called ALLOW_RETRIES. This keyword
takes a single integer as an argument, and it allows the test to fail that
number of times before it first succeeds.

This work attempts to make the existing test_retry_attempts more flexible
by allowing by-test customization, as well as eliminate libc++'s FLAKY_TEST
custom logic.

Differential Revision: https://reviews.llvm.org/D76288
2020-03-18 18:04:01 -04:00
Alexey Bataev f3c857fae2 [OPENMP50]Add basic codegen support for ancestor device modifier.
If the ancestor device modifier is used and the value of the device
clause is evaluated to 1, the ancestor device shall be used for the
execution.
Since the reverse offloading is not supported yet, the target construct
execution is always initiated from the host, not from the device. So, if
the ancestor modifier is specified, just execute target region on the
host.
2020-03-18 17:53:18 -04:00
Simon Pilgrim 99336bf95a [ValueTracking] Add computeKnownBits DemandedElts support to masked add instructions (PR36319) 2020-03-18 21:50:56 +00:00
Eric Schweitz 7b5d4669da [MLIR] Allow global with an external linkage to include initial value
Reviewers: rriddle, ftynse

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D76333
2020-03-18 14:46:54 -07:00
Davide Italiano 85bd436961 [Host] Remove some code that's not needed anymore.
Discussed offline with Jason.
2020-03-18 14:44:53 -07:00
Florian Hahn fd2c15e602 [VPlan] Do not print mapping for Value2VPValue.
The latest improvements to VPValue printing make this mapping clear when
printing the operand. Printing the mapping separately is not required
any longer.

Reviewers: rengolin, hsaito, Ayal, gilr

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D76375
2020-03-18 21:44:07 +00:00
Hanhan Wang ae7bda5dac [mlir][Linalg] Remove initial value for conditions.
Summary:
Although bool and int1 are the same sometimes, using bool constant matches the
semantic better. In any cases, we don't have to care the type of conditions if
we remove the intial value. The type is determined automatically by the returned
type of logical operations.

Differential Revision: https://reviews.llvm.org/D76338
2020-03-18 14:42:21 -07:00
Alex Cameron 9bb5685b21 [clang-tidy] misc-unconventional-assign-operator suggest to use rvalue references in C++03 mode
Summary:
Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=27702
I wasn't sure how this type of thing is usually tested. So any advice would be appreciated.
`check-llvm`, `check-clang` and `check-clang-tools` are clean for me.
**C++98**
```
tetsuo@garland-c-16-sgp1-01:~/dev/llvm-project/test$ cat compile_commands.json
[
{
  "directory": "/home/tetsuo/dev/llvm-project/test",
  "command": "/usr/bin/c++      -std=gnu++98 -o CMakeFiles/test.dir/test.cpp.o -c /home/tetsuo/dev/llvm-project/test/test.cpp",
  "file": "/home/tetsuo/dev/llvm-project/test/test.cpp"
}
]
tetsuo@garland-c-16-sgp1-01:~/dev/llvm-project/test$ ../build/bin/clang-tidy --checks=misc-unconventional-assign-operator test.cpp
3053 warnings generated.
/home/tetsuo/dev/llvm-project/test/test.cpp:7:3: warning: operator=() should take 'Foo const&' or 'Foo' [misc-unconventional-assign-operator]
  Foo &operator=(Foo &Other) {
  ^
Suppressed 3052 warnings (3052 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
```
**C++17**
```
tetsuo@garland-c-16-sgp1-01:~/dev/llvm-project/test$ cat compile_commands.json
[
{
  "directory": "/home/tetsuo/dev/llvm-project/test",
  "command": "/usr/bin/c++      -std=gnu++17 -o CMakeFiles/test.dir/test.cpp.o -c /home/tetsuo/dev/llvm-project/test/test.cpp",
  "file": "/home/tetsuo/dev/llvm-project/test/test.cpp"
}
]
tetsuo@garland-c-16-sgp1-01:~/dev/llvm-project/test$ ../build/bin/clang-tidy --checks=misc-unconventional-assign-operator test.cpp
5377 warnings generated.
/home/tetsuo/dev/llvm-project/test/test.cpp:7:3: warning: operator=() should take 'Foo const&', 'Foo&&' or 'Foo' [misc-unconventional-assign-operator]
  Foo &operator=(Foo &Other) {
  ^
Suppressed 5376 warnings (5376 in non-user code).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
```

Reviewers: njames93, MaskRay, alexfh, hokein, aaron.ballman

Reviewed By: njames93

Subscribers: xazax.hun, cfe-commits

Tags: #clang-tools-extra, #clang

Differential Revision: https://reviews.llvm.org/D75901
2020-03-18 21:39:23 +00:00
Florian Hahn 00c1cd1934 [VPlan] Record underlying value for VPValues created by addVPValue (NFC).
Now that printing VPValues uses the underlying IR value name, if
available, recording the underlying value here improves printing.

Reviewers: rengolin, hsaito, Ayal, gilr

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D76374
2020-03-18 21:30:58 +00:00
Sanjay Patel acaf144222 [LangRef] fix formatting tick; NFC 2020-03-18 17:26:41 -04:00
Sanjay Patel faba1d034a [LangRef] add explanatory text for select poison semantics (PR20895)
This is copied from the suggested text by @regehr in:
https://bugs.llvm.org/show_bug.cgi?id=20895

The way forward was not clear for several years, but now that we
have 'freeze' and Alive2, the behavior should be documented.
Also see comments in D76332.
2020-03-18 17:17:20 -04:00
Yunlian Jiang 30ccc2e8d2 [libc++] Add missing visibility annotation for __base
Differential Revision: https://reviews.llvm.org/D48680
2020-03-18 17:16:00 -04:00
Simon Pilgrim 49bdfd888d [InstSimplify] Add missing vector masked add tests to show lack of DemandedElts support 2020-03-18 21:04:54 +00:00
Eli Friedman e24e95fe90 Remove CompositeType class.
The existence of the class is more confusing than helpful, I think; the
commonality is mostly just "GEP is legal", which can be queried using
APIs on GetElementPtrInst.

Differential Revision: https://reviews.llvm.org/D75660
2020-03-18 13:53:17 -07:00
Petr Hosek c682a605eb [Fuchsia] Include llvm-gsymutil tool in the Fuchsia toolchain
This tool is used for generating and manipulating GSYM files.

Differential Revision: https://reviews.llvm.org/D76204
2020-03-18 13:51:47 -07:00
Sanjay Patel 22c66c1a28 [JumpThreading] add a miscompile test based on discussion in D76332; NFC 2020-03-18 16:46:18 -04:00
Craig Topper 498b53890d [SelectionDAGBuilder][FPEnv] Take into account SelectionDAG continuous CSE when setting the nofpexcept flag for constrained intrinsics
SelectionDAG CSEs nodes based on their result type and operands, but not their flags. The flags are expected to be intersected when they are CSEd. In SelectionDAGBuilder, for FP nodes we manage both the fast math flags and the nofpexcept flag after the nodes have already been CSEd when they were created with getNode. The management of the fastmath flags before the constrained nodes prevents the nofpexcept management from working correctly.

This commit moves the FMF handling for constrained intrinsics into their visitor and disables the common FMF handling for these nodes.

Differential Revision: https://reviews.llvm.org/D75224
2020-03-18 13:37:17 -07:00
River Riddle 64a5e57a61 [mlir] Disable notifyMatchFailure in NDEBUG
Summary: The usage story in for NDEBUG isn't fleshed out yet, so this revision ensures that none of the diagnostic code exists in the binary.

Differential Revision: https://reviews.llvm.org/D76372
2020-03-18 13:27:04 -07:00
Simon Pilgrim 9d40292a64 [ValueTracking] Add computeKnownBits DemandedElts support to XOR instructions (PR36319) 2020-03-18 20:24:14 +00:00
Simon Pilgrim 47ce1406c8 [InstSimplify] Add missing vector OR test to show lack of DemandedElts support 2020-03-18 20:24:14 +00:00
Simon Pilgrim 6bdb0efa42 [InstSimplify] Regenerate OR tests 2020-03-18 20:24:13 +00:00
Nicolas Vasilache 1e43132209 [mlir][LLVM] Add masked reads and writes.
Summary: These intrinsics will be used to lower vector transfer read/write.

Reviewers: aartbik, tetuante, jsetoain

Reviewed By: aartbik

Subscribers: mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D75986
2020-03-18 16:19:07 -04:00
Fred Riss b40ee7ff1b [lldb/MemoryHistoryAsan] Fix address resolution for recorded backtraces
Summary:
The memory history plugin for Asan creates a HistoryThread with the
recorded PC values provided by the Asan runtime. In other cases,
thoses PCs are gathered by LLDB directly.

The PCs returned by the Asan runtime are the PCs of the calls in the
backtrace, not the return addresses you would normally get when
unwinding the stack (look for a call to GetPreviousIntructionPc in
AsanGetStack).

When the above addresses are passed to the unwinder, it will subtract
1 from each address of the non zero frames because it treats them as
return addresses. This can lead to the final report referencing the
wrong line.

This patch fixes this issue by threading a flag through HistoryThread
and HistoryUnwinder that tells them to treat every frame like the
first one. The Asan MemoryHistory plugin can then use this flag.

This fixes running TestMemoryHistory on arm64 devices, although it's
hard to guarantee that the test will continue to exhibit the boundary
condition that triggers this bug.

Reviewers: jasonmolenda, kubamracek

Subscribers: kristof.beyls, danielkiss, lldb-commits

Tags: #lldb

Differential Revision: https://reviews.llvm.org/D76341
2020-03-18 13:18:02 -07:00
River Riddle 4be504a97f [mlir] Add support for detecting single use callables in the Inliner.
Summary: This is somewhat complex(annoying) as it involves directly tracking the uses within each of the callgraph nodes, and updating them as needed during inlining. The benefit of this is that we can have a more exact cost model, enable inlining some otherwise non-inlinable cases, and also ensure that newly dead callables are properly disposed of.

Differential Revision: https://reviews.llvm.org/D75476
2020-03-18 13:10:41 -07:00
lewis-revill e9f22fd429 [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes
This patch generates TableGen descriptions for the specified register
banks which contain a list of register sizes corresponding to the
available HwModes. The appropriate size is used during codegen according
to the current HwMode. As this HwMode was not available on generation,
it is set upon construction of the RegisterBankInfo class. Targets
simply need to provide the HwMode argument to the
<target>GenRegisterBankInfo constructor.

The RISC-V RegisterBankInfo constructor has been updated accordingly
(plus an unused argument removed).

Differential Revision: https://reviews.llvm.org/D76007
2020-03-18 19:52:23 +00:00
lewis-revill e225e770f7 [TableGen][GlobalISel] Rework RegisterBankEmitter for easier const correctness.
This patch rewrites the RegisterBankEmitter class to derive
RegisterClassHierarchy from CodeGenTarget::getRegBank() rather than
constructing our own copy. All are now accessed through a const
reference.

Differential Revision: https://reviews.llvm.org/D76006
2020-03-18 19:52:23 +00:00