Sjoerd Meijer
|
2a57b357a3
|
[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction.
Differential Revision: https://reviews.llvm.org/D48918
llvm-svn: 336418
|
2018-07-06 08:03:12 +00:00 |