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16 Commits

Author SHA1 Message Date
Florian Hahn cc524bf6ac [CodeGen] Add thumb-mode to target-features for arm/thumb triples. 
Summary:
The thumb-mode target feature is used to force Thumb or ARM code
generation on a per-function basis. Explicitly adding +thumb-mode to
functions for thumbxx triples enables mixed ARM/Thumb code generation in
places where compilation units with thumbxx and armxx triples are merged
together (e.g. the IR linker or LTO).

For armxx triples, -thumb-mode is added in a similar fashion.

Reviewers: echristo, t.p.northover, kristof.beyls, rengolin

Reviewed By: echristo

Subscribers: rinon, aemerson, mehdi_amini, javed.absar, cfe-commits

Differential Revision: https://reviews.llvm.org/D33448

llvm-svn: 304897
 2017-06-07 11:50:45 +00:00
Evandro Menezes ba17775c84 Add support for Samsung Exynos M3 (NFC) 
llvm-svn: 289614
 2016-12-13 23:31:57 +00:00
Evandro Menezes ec133b3d20 [AArch64] Add support for Samsung Exynos M2 (NFC). 
llvm-svn: 277365
 2016-08-01 18:39:55 +00:00
Sjoerd Meijer 90df4a7c31 This adds target support and tests for Cortex-A73 
Differential Revision: http://reviews.llvm.org/D20864

llvm-svn: 271507
 2016-06-02 10:48:37 +00:00
Renato Golin 930de67e6a [ARM] Clang tests for ARM Cortex-A32 support 
Patch by Sam Parker.

llvm-svn: 263957
 2016-03-21 17:29:51 +00:00
Pablo Barrio 2a35ff0687 Add more ARM Cortex-R8 regression tests to Clang. 
Summary:
This patch adds Clang tests for Cortex-R8 related to FP capabilities and
hardware integer divide.

Reviewers: rengolin, bsmith

Subscribers: aemerson, cfe-commits, rengolin

Differential Revision: http://reviews.llvm.org/D18193

llvm-svn: 263632
 2016-03-16 10:21:04 +00:00
MinSeong Kim 50d9c156dd [AArch64] Teaches clang about Samsung Exynos-M1 
Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A).

Differential Revision: http://reviews.llvm.org/D15664

llvm-svn: 256829
 2016-01-05 12:53:24 +00:00
Christof Douma ba13ad58f7 Teaches clang about Cortex-A35. 
Adds support for the new Cortex-A35 ARMv8-A core.

Differential Revision: http://reviews.llvm.org/D15142

llvm-svn: 254505
 2015-12-02 12:03:42 +00:00
Artyom Skrobov 05d85aee2e [ARM] Renaming +t2dsp feature into +dsp, as discussed on llvm-dev 
llvm-svn: 251124
 2015-10-23 17:19:02 +00:00
Artyom Skrobov d3ae09bcc8 Recommit r248154: [ARM] Handle DSP feature as an ArchExtKind 
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in
a hand-rolled tricky condition block in lib/Basic/Targets.cpp, with a FIXME:
attached.

http://reviews.llvm.org/D12937 moved the handling of the DSP feature over to
ARMTargetParser.def in LLVM, to be in line with other architecture extensions.

This is the corresponding patch to clang, to clear the FIXME: and update
the tests.

Differential Revision: http://reviews.llvm.org/D12938

llvm-svn: 248521
 2015-09-24 17:34:05 +00:00
James Molloy 93bd4e9979 Revert "[ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def" 
This was committed without the code review (http://reviews.llvm.org/D12938) being approved.

This reverts commit r248154.

llvm-svn: 248173
 2015-09-21 16:34:58 +00:00
Artyom Skrobov 7428f1ef64 [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.def 
Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in
a hand-rolled tricky condition block in lib/Basic/Targets.cpp, with a FIXME:
attached.

http://reviews.llvm.org/D12937 moved the handling of +t2dsp over to
ARMTargetParser.def in LLVM, to be in line with other architecture extensions.

This is the corresponding patch to clang, to clear the FIXME: and update
the tests.

Differential Revision: http://reviews.llvm.org/D12938

llvm-svn: 248154
 2015-09-21 13:19:25 +00:00
Alexandros Lamprineas 3834d2ca08 [ARM] "cortex-r5f" and "cortex-m4f" are unknown names for clang. 
The tests in test/CodeGen/arm-target-features.c are currently
passing but warning messages are suppressed. These tests are now
synchronized with the corresponding changes in Target Parser.

This patch will fix the regressions in clang caused by r247136

Differential Revision: http://reviews.llvm.org/D12722

llvm-svn: 247138
 2015-09-09 11:29:06 +00:00
Alexandros Lamprineas 94d75dba14 Refactoring of how ARMTargetInfo handles default target features. 
Differential Revision: http://reviews.llvm.org/D11299

llvm-svn: 246946
 2015-09-06 16:15:45 +00:00
Eric Christopher 2374a7cba8 Use a stable sort to guarantee target feature ordering in the IR 
in order to make testing somewhat more feasible. Has the advantage
of making it easier to find target features as well.

llvm-svn: 241134
 2015-07-01 01:07:12 +00:00
Tim Northover f9b517c159 ARM: merge Cyclone into other ARMv8 CPUs and add tests for features. 
Cyclone actually supports all the goodies you'd expect to come with an AArch64
CPU, so it doesn't need its own clause. Also we should probably be testing
these clauses.

llvm-svn: 236349
 2015-05-01 21:17:25 +00:00