d3c8319f48
Add some dummy support for post-incremented loads
...
llvm-svn: 86385
2009-11-07 17:15:06 +00:00
f93bb39b03
Add 8 bit libcalls and make use of them for msp430
...
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
2a88785685
Initial support for addrmode handling. Tests by Brian Lucas!
...
llvm-svn: 86382
2009-11-07 17:13:35 +00:00
226467d6a6
It turns out that the testcase in question uncovered subreg-handling bug.
...
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
bd05185ef1
Fix a couple of shuffle patterns to use movhlps instead
...
of movhps as the constraint. Changes optimizations so
update testcases as appropriate as well.
llvm-svn: 86360
2009-11-07 08:45:53 +00:00
8e1d7222a7
Fix PR5421 by APInt'izing switch lowering.
...
llvm-svn: 86354
2009-11-07 07:50:34 +00:00
74ab6efbe8
merge cmp1 into cmp0 and filecheckize.
...
llvm-svn: 86345
2009-11-07 06:19:20 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
...
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
7ff831962a
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
...
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
207b246650
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
...
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
9df3acf486
Honour subreg machine operands during asmprinting
...
llvm-svn: 86303
2009-11-06 23:45:15 +00:00
d95ccd6c4d
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
...
will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
db42ca663b
Fix a broken test.
...
llvm-svn: 86298
2009-11-06 23:06:42 +00:00
408aa56fb5
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
...
llvm-svn: 86294
2009-11-06 22:24:13 +00:00
80f04dc67d
Fix PR5315, original patch by Nicolas Capens!
...
llvm-svn: 86203
2009-11-06 00:11:57 +00:00
98693a3ac2
Update these tests for the new label names.
...
llvm-svn: 86192
2009-11-05 23:31:40 +00:00
45119d8850
Add -mtriple to llc commands, attempting to fix buildbot failures.
...
llvm-svn: 86086
2009-11-05 00:51:31 +00:00
90d0b82e12
Attempt again to fix buildbot failures: make expected output less specific
...
and compile with -mtriple to specify *-apple-darwin targets.
llvm-svn: 86081
2009-11-05 00:30:35 +00:00
f84f7105f7
Add PowerPC codegen for indirect branches.
...
llvm-svn: 86050
2009-11-04 21:31:18 +00:00
e8ca96cf24
Fix broken test.
...
llvm-svn: 86045
2009-11-04 20:04:11 +00:00
16f60b9216
Add test for ARM indirectbr codegen.
...
llvm-svn: 86042
2009-11-04 19:25:34 +00:00
95bdc5d899
RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
...
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.
llvm-svn: 86022
2009-11-04 08:33:14 +00:00
8f4e3d99c9
Fix test.
...
llvm-svn: 85986
2009-11-04 00:42:33 +00:00
0410bced1c
fconsts / fconstd immediate should be proceeded with #.
...
llvm-svn: 85952
2009-11-03 21:59:33 +00:00
f42b5af549
Re-apply 85799. It turns out my code isn't buggy.
...
llvm-svn: 85947
2009-11-03 21:40:02 +00:00
90fedc6ef9
Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test
...
llvm-svn: 85900
2009-11-03 15:29:06 +00:00
8d681f0471
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
...
llvm-svn: 85871
2009-11-03 05:52:54 +00:00
a21bc75d78
Declare sin & cos as readonly so they match the code in SelectionDAGBuild
...
llvm-svn: 85853
2009-11-03 02:19:31 +00:00
2c2dc9f64f
Temporary xfail until PR5367 will be resolved
...
llvm-svn: 85848
2009-11-03 00:37:36 +00:00
fbe0256b23
Revert r85049, it is causing PR5367
...
llvm-svn: 85847
2009-11-03 00:24:48 +00:00
a8a58efc03
Revert 85799 for now. It might be breaking llvm-gcc driver.
...
llvm-svn: 85827
2009-11-02 21:49:14 +00:00
2729543984
Initilize the machine LICM CSE map upon the first time an instruction is hoisted to
...
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.
llvm-svn: 85799
2009-11-02 08:09:49 +00:00
fb2d385221
Remove an irrelevant and poorly reduced test case.
...
llvm-svn: 85794
2009-11-02 07:11:54 +00:00
1708b06c0e
Unbreak ARMBaseRegisterInfo::copyRegToReg.
...
llvm-svn: 85787
2009-11-02 04:44:55 +00:00
4d23754b14
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
...
llvm-svn: 85767
2009-11-02 00:12:06 +00:00
8cce1eb6aa
64-bit FP loads & stores operate on both NEON and VFP pipelines.
...
llvm-svn: 85765
2009-11-02 00:11:06 +00:00
43219997b6
Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.
...
llvm-svn: 85743
2009-11-01 21:12:51 +00:00
50bc004b67
Fix tests.
...
llvm-svn: 85723
2009-11-01 18:13:29 +00:00
50ba5c3dc2
improve x86 codegen support for blockaddress. We now compile
...
the testcase into:
_test1: ## @test1
## BB#0: ## %entry
leaq L_test1_bb6(%rip), %rax
jmpq *%rax
L_test1_bb: ## Address Taken
LBB1_1: ## %bb
movb $1, %al
ret
L_test1_bb6: ## Address Taken
LBB1_2: ## %bb6
movb $2, %al
ret
Note, it is very very strange that BlockAddressSDNode doesn't carry
around TargetFlags. Dan, please fix this.
llvm-svn: 85703
2009-11-01 03:25:03 +00:00
6f29ad9170
Use cbz and cbnz instructions.
...
llvm-svn: 85698
2009-10-31 23:46:45 +00:00
5cba8de2c8
vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using
...
them for scalar floating point operations for now.
llvm-svn: 85697
2009-10-31 22:57:36 +00:00
403202aef1
Consolidate test files
...
llvm-svn: 85696
2009-10-31 22:20:56 +00:00
c79fb530d4
Change to use FileCheck
...
llvm-svn: 85695
2009-10-31 22:16:14 +00:00
69f364babc
Make tests more explicit about which instructions are expected.
...
llvm-svn: 85694
2009-10-31 22:14:17 +00:00
259c37cc55
Grammar tweak to comments
...
llvm-svn: 85693
2009-10-31 22:12:44 +00:00
2c3e618a06
Update test to be more explicit about what instruction sequences are expected for each operation.
...
llvm-svn: 85691
2009-10-31 22:10:38 +00:00
0de95af62d
Update test to be more explicit about what instruction sequences are expected for each operation.
...
llvm-svn: 85689
2009-10-31 21:52:58 +00:00
8fe6fd702d
Expand 64-bit logical shift right inline
...
llvm-svn: 85687
2009-10-31 21:42:19 +00:00
624fcb286e
Expand 64-bit arithmetic shift right inline
...
llvm-svn: 85685
2009-10-31 21:00:56 +00:00
6ef6fe1c31
Force triple; darwin's ASM syntax differs from linux's.
...
llvm-svn: 85676
2009-10-31 19:54:06 +00:00
5d994048dd
Expand 64 bit left shift inline rather than using the libcall. For now, this
...
is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
llvm-svn: 85675
2009-10-31 19:38:01 +00:00
7e06083a3a
Add missing colons for FileCheck.
...
llvm-svn: 85674
2009-10-31 19:22:24 +00:00
bf1cb1343f
Convert to FileCheck
...
llvm-svn: 85673
2009-10-31 19:06:53 +00:00
cdbb70c065
It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to enable more machine licm. More changes coming.
...
llvm-svn: 85643
2009-10-31 03:39:36 +00:00
ea88910dbf
Add a target triple so that this test behaves consistently across hosts.
...
llvm-svn: 85640
2009-10-31 00:15:28 +00:00
10eed3788d
Fix the -mattr line for this test so that it passes on hosts that lack SSSE3.
...
llvm-svn: 85637
2009-10-30 23:18:27 +00:00
49fa51d936
Fix MachineLICM to use the correct virtual register class when
...
unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the
opcode of the original operation without the load, not the load
itself, MachineLICM needs to know the operand index in order to get
the correct register class. Extend getOpcodeAfterMemoryUnfold to
return this information.
llvm-svn: 85622
2009-10-30 22:18:41 +00:00
28f052fc89
I forgot to commit this test.
...
llvm-svn: 85608
2009-10-30 20:03:40 +00:00
ab7c709f43
This fixes functions like
...
void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
llvm-svn: 85590
2009-10-30 14:33:14 +00:00
3ab552ec74
Reimplement BranchFolding change to avoid tail merging for a 1 instruction
...
common tail, except when the OptimizeForSize function attribute is present.
Radar 7338114.
llvm-svn: 85441
2009-10-28 22:10:20 +00:00
1b44f10ff4
Teach MachineLICM to unfold loads from constant memory from
...
otherwise unhoistable instructions in order to allow the loads
to be hoisted.
llvm-svn: 85364
2009-10-28 03:21:57 +00:00
4a609f3cef
Use fconsts and fconstd to materialize small fp constants.
...
llvm-svn: 85362
2009-10-28 01:44:26 +00:00
4b46cbfc23
Mark dead physregdefs dead immediately. This helps MachineSink and
...
MachineLICM and other things which run before LiveVariables is run.
llvm-svn: 85360
2009-10-28 01:13:53 +00:00
75d6a4afd2
Allow constants of different types to share constant pool entries
...
if they have compatible encodings.
llvm-svn: 85359
2009-10-28 01:12:16 +00:00
d92a3633e1
Add missing testcase.
...
llvm-svn: 85266
2009-10-27 17:59:03 +00:00
3d43b38f0f
Fix Thumb2 failures by converting them to FileCheck.
...
llvm-svn: 85210
2009-10-27 06:31:02 +00:00
d169e6c281
Fix the rest of the ARM failures by converting them to FileCheck.
...
llvm-svn: 85208
2009-10-27 06:16:45 +00:00
04580c8307
Fix some more failures by converting to FileCheck.
...
llvm-svn: 85207
2009-10-27 05:50:28 +00:00
e8d20795a3
Convert to FileCheck, fixing failure due to tab change in the process.
...
llvm-svn: 85204
2009-10-27 05:30:47 +00:00
8370485db9
Break anti-dependence breaking out into its own class.
...
llvm-svn: 85127
2009-10-26 16:59:04 +00:00
d632f89596
Make LSR's OptimizeShadowIV ignore induction variables with negative
...
strides for now, because it doesn't handle them correctly. This fixes a
miscompile of SingleSource/Benchmarks/Misc-C++/ray.
This problem was usually hidden because indvars transforms such induction
variables into negations of canonical induction variables.
llvm-svn: 85118
2009-10-26 15:32:57 +00:00
b81cb2a9a8
- Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and
...
bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
common for targets to operate on registers where the top bits are undef. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
= d0
When the insert_subreg is eliminated by the coalescer, the scavenger used to
complain. The previous fix was to keep to insert_subreg around. But that's
brittle and it's overly conservative when we want to use the scavenger to
allocate registers. It's actually legal and desirable for other instructions
to use the "undef" part of d0. e.g.
s0 =
d0 = insert_subreg d0<undef>, s0, 1
...
s1 =
= s1
= d0
We probably need add a "partial-undef" marker on machine operand so the
machine verifier would not complain.
llvm-svn: 85091
2009-10-26 04:56:07 +00:00
e38317f432
fix PR5295 where the .ll parser didn't reject a function after a global
...
or global after a function with conflicting names. Update some testcases
that were accidentally depending on this behavior.
llvm-svn: 85081
2009-10-25 23:22:50 +00:00
69140ec4fa
Add a couple of ARM cross-rc coalescing tests.
...
llvm-svn: 85051
2009-10-25 08:01:41 +00:00
b9f3520660
Update tests.
...
llvm-svn: 85050
2009-10-25 07:53:48 +00:00
4ef112be62
APInt-ify the gep scaling code, so that it correctly handles the case where
...
the scale overflows pointer-sized arithmetic. This fixes PR5281.
llvm-svn: 84954
2009-10-23 17:57:43 +00:00
36f4bd0b62
Update tests for 84931.
...
llvm-svn: 84932
2009-10-23 05:58:34 +00:00
02ad4cb32e
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
...
llvm-svn: 84911
2009-10-22 23:19:17 +00:00
9d763cc3f8
Revert 84843. Evan, this was breaking some of the if-conversion tests.
...
llvm-svn: 84868
2009-10-22 16:52:21 +00:00
3615b9bef3
Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.
...
llvm-svn: 84843
2009-10-22 06:48:32 +00:00
0f55e9ce2e
Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
...
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
f1ad2c618a
Use special DAG-to-DAG preprocessing to allow mem-mem instructions to be selected.
...
Yay for ASCII graphics!
llvm-svn: 84808
2009-10-22 00:16:00 +00:00
ff97acd8f1
Revert the main portion of r31856. It was causing BranchFolding
...
to break up CFG diamonds by banishing one of the blocks to the end of
the function, which is bad for code density and branch size.
This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the
benchmark cited as the reason for the change, however I've examined
the code and it looks more like a case of gaming a particular
branch than of being generally applicable.
llvm-svn: 84803
2009-10-22 00:03:58 +00:00
a93ca3c637
Improve handling of immediates by splitting 32-bit immediates into two 16-bit
...
immediate operands when they will fit into the using instruction.
llvm-svn: 84778
2009-10-21 20:44:34 +00:00
9e92857b38
Add DAG printing for RMW stuff debugging
...
llvm-svn: 84776
2009-10-21 19:18:28 +00:00
ccfa3e31f7
RMW preprocessing stuff was incorrect. Grab the stuff from x86 backend and disable some tests until it will be clever enough to handle them.
...
llvm-svn: 84775
2009-10-21 19:17:55 +00:00
786b15fe12
Match more patterns to movt.
...
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
682a2d154a
Revert r84658 and r84691. They were causing llvm-gcc bootstrap to fail.
...
llvm-svn: 84727
2009-10-21 01:44:44 +00:00
7cea91e171
Add reg-imm tests
...
llvm-svn: 84705
2009-10-21 00:11:44 +00:00
a6faf60831
Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)
...
transform.
llvm-svn: 84683
2009-10-20 21:37:45 +00:00
baf6dd26ea
Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.
...
llvm-svn: 84658
2009-10-20 19:54:44 +00:00
4a43e3068d
Make TranslateX86CC return COND_INVALID instead of aborting when it
...
encounters an OEQ or UNE comparison, and update its callers to check
for this return status and recover. This fixes a problem resulting from
the LowerOperation hooks being called from LegalizeVectorOps, because
LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may
still be at large. This fixes PR5092.
llvm-svn: 84640
2009-10-20 16:22:37 +00:00
c0964a571b
Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks are
...
tracked. Instead of trying to manually keep track of these locations
while doing complex modifications, just recompute them when they're needed.
This fixes a bug in which the TopMBB and BotMBB were not correctly updated,
leading to invalid transformations.
llvm-svn: 84598
2009-10-20 04:50:37 +00:00
fa4bcaec7c
If the physical register being spilled does not have an interval, spill its sub-registers instead.
...
llvm-svn: 84586
2009-10-20 01:31:09 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
...
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
0ed889521b
convert to filecheck syntax and make a lot more aggressive.
...
llvm-svn: 84517
2009-10-19 18:27:56 +00:00
8383c3d7f3
Revert r84295, this unbreaks llvm-gcc bootstrap on x86-64/linux
...
llvm-svn: 84516
2009-10-19 18:21:09 +00:00
7ea0c35ba0
rename test
...
llvm-svn: 84515
2009-10-19 18:18:07 +00:00
033f01c922
Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
...
LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.
llvm-svn: 84485
2009-10-19 11:00:58 +00:00
1df7ea05c3
Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' aren't tests.
...
llvm-svn: 84460
2009-10-19 03:53:55 +00:00
18df82a20c
Add support for matching shuffle patterns with palignr.
...
llvm-svn: 84459
2009-10-19 02:17:23 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
...
llvm-svn: 84431
2009-10-18 19:57:27 +00:00
0d3d9ee03e
Enhance CodePlacementOpt's unconditional intra-loop branch elimination logic
...
to be more general and understand more varieties of loops.
Teach CodePlacementOpt to reorganize the basic blocks of a loop so that
they are contiguous. This also includes a fair amount of logic for preserving
fall-through edges while doing so. This fixes a BranchFolding-ism where blocks
which can't be made to use a fall-through edge and don't conveniently fit
anywhere nearby get tossed out to the end of the function.
llvm-svn: 84295
2009-10-17 00:32:43 +00:00
1a015acf69
Update tests to use FileCheck
...
llvm-svn: 84282
2009-10-16 22:09:05 +00:00
0185b1ea85
Add test case for r84279
...
llvm-svn: 84280
2009-10-16 22:07:19 +00:00
99429a00ff
Move zext and sext casts fed by loads into the same block as the
...
load, to help SelectionDAG fold them into the loads, unless
conditions are unfavorable.
llvm-svn: 84271
2009-10-16 20:59:35 +00:00
03da4dba59
Enable post-alloc scheduling for all ARM variants except for Thumb1.
...
llvm-svn: 84249
2009-10-16 06:11:08 +00:00
3f23601b00
Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
...
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
a07cae65e3
Re-apply 84180 with the fixed test case.
...
llvm-svn: 84195
2009-10-15 19:26:25 +00:00
460ceae432
Move Blackfin intrinsics into the Target/Blackfin directory.
...
llvm-svn: 84194
2009-10-15 18:50:52 +00:00
c9af381df8
Make CodePlacementOpt align loops, rather than loop headers. The
...
header is just the entry block to the loop, and it needn't be at
the top of the loop in the code layout.
Remove the code that suppressed loop alignment for outer loops,
so that outer loops are aligned.
llvm-svn: 84158
2009-10-15 00:36:22 +00:00
2f61e0946a
When LiveVariables is adding implicit-def to model "partial dead", add the earlyclobber marker if the superreg def has it.
...
llvm-svn: 84153
2009-10-14 23:39:27 +00:00
03a7667349
Fix this test to account for a movl $0 being emitted as an xor now,
...
and convert it to FileCheck.
llvm-svn: 84065
2009-10-14 00:28:48 +00:00
3b51560ae4
Revise ARM inline assembly memory operands to require the memory address to
...
be in a register. The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb. Radar 7137468.
llvm-svn: 84022
2009-10-13 20:50:28 +00:00
423e42b371
Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
...
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
a698d7ac3c
Don't forget to mark RAX as live-out of the function when arranging for
...
it to hold the address of an sret return value, for x86-64 ABI purposes.
Also, fix the test that was originally intended to test this to actually
test it, using FileCheck.
llvm-svn: 83853
2009-10-12 16:36:12 +00:00
258c7fa33a
Eliminate some redundant llvm-as calls.
...
llvm-svn: 83837
2009-10-12 09:31:55 +00:00
4b38ce9f25
Add missed mem-mem move patterns
...
llvm-svn: 83812
2009-10-11 23:03:53 +00:00
415c3dc501
Add MSP430 mem-mem insts support. Patch by Brian Lucas with some my refinements
...
llvm-svn: 83811
2009-10-11 23:03:28 +00:00
da0508fe15
Add bunch of MSP430 'feature' tests. Patch by Brian Lucas with some my refinements
...
llvm-svn: 83809
2009-10-11 23:02:38 +00:00
6bce6bbf40
Implement 'm' memory operand properly
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llvm-svn: 83785
2009-10-11 19:14:21 +00:00
5b8826b4da
It seems that OR operation does not affect status reg at all.
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Remove impdef of SRW. This fixes PR4779
llvm-svn: 83739
2009-10-10 22:17:47 +00:00
50998f4584
Update this test; the code is the same but it gets counted as one
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fewer remat.
llvm-svn: 83690
2009-10-09 23:31:04 +00:00
7d9dffb413
Fix the x86 test-shrink optimization so that it doesn't shrink comparisons
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when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.
llvm-svn: 83670
2009-10-09 20:35:19 +00:00
35b6173a17
Merge a bunch of NEON tests into larger files so they run faster.
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llvm-svn: 83667
2009-10-09 20:20:54 +00:00
6dd3b9ad58
Convert some ARM tests with lots of greps to use FileCheck.
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llvm-svn: 83651
2009-10-09 17:20:46 +00:00
ccd4545ecb
Fix a logic error that caused non-rematable loop invariants loads to be licm'ed out of loop.
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llvm-svn: 83622
2009-10-09 06:21:52 +00:00
e9b19f76cb
Commit one last NEON test to use FileCheck. That's all of them now!
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llvm-svn: 83617
2009-10-09 05:31:56 +00:00
24b84fecf2
Convert more NEON tests to use FileCheck.
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llvm-svn: 83616
2009-10-09 05:14:48 +00:00
be27d61cbc
Reset kill markers after live interval is reconstructed.
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llvm-svn: 83608
2009-10-09 01:17:11 +00:00
84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
1fd98d67e3
Convert more NEON tests to use FileCheck.
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llvm-svn: 83595
2009-10-08 23:33:03 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
f448255063
Convert more NEON tests to use FileCheck.
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llvm-svn: 83587
2009-10-08 22:33:53 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
222b86cd54
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
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llvm-svn: 83572
2009-10-08 20:43:22 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
7d94eb4722
Convert more NEON tests to use FileCheck.
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llvm-svn: 83528
2009-10-08 06:02:10 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
d1de3b82ff
Convert more NEON tests to use FileCheck.
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llvm-svn: 83507
2009-10-07 23:47:21 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
e32fe29d29
Fix handling of x86 'R' constraint.
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llvm-svn: 83499
2009-10-07 22:47:20 +00:00
6d850f294d
Convert more NEON tests to use FileCheck.
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llvm-svn: 83497
2009-10-07 22:30:19 +00:00
Anton Korobeynikov