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Author SHA1 Message Date
Jim Grosbach 805d195649 Cleanup. Missed removing these when converting. Oops. 
llvm-svn: 89001
 2009-11-17 00:00:33 +00:00
Dan Gohman b43e1ff236 Fix this test - there don't appear to be any actual Reload Reuses 
in this testcase.

llvm-svn: 88998
 2009-11-16 23:49:55 +00:00
Dan Gohman 9dede3b383 Revert r87049, which was the workaround for the regression triggered 
by the recent FixedStackPseudoSourceValue-related changes, now that
the specific bug that affected it is fixed, in r88954.

llvm-svn: 88997
 2009-11-16 23:43:42 +00:00
Jim Grosbach 1deb0b9f53 Convert to FileCheck 
llvm-svn: 88991
 2009-11-16 23:19:29 +00:00
Evan Cheng f25ef4ffb0 - Check memoperand alignment instead of checking stack alignment. Most load / store folding instructions are not referencing spill stack slots. 
- Mark MOVUPSrm re-materializable.

llvm-svn: 88974
 2009-11-16 21:56:03 +00:00
Jim Grosbach 9b32e22ad1 Convert to FileCheck 
llvm-svn: 88947
 2009-11-16 20:04:15 +00:00
Lang Hames 16f6b3e607 Added a testcase for PR5495. 
llvm-svn: 88946
 2009-11-16 20:03:13 +00:00
Jim Grosbach 980d94164d Convert to FileCheck 
llvm-svn: 88942
 2009-11-16 19:46:46 +00:00
Jim Grosbach c670bdc311 tbb opt off by default 
llvm-svn: 88921
 2009-11-16 17:24:45 +00:00
David Greene 25905c8336 Support spill comments. 
Have the asm printer emit a comment if an instruction is a spill or
reload and have the spiller mark copies it introdues so the asm printer
can also annotate those.

llvm-svn: 88911
 2009-11-16 15:12:23 +00:00
Evan Cheng 597f7b6ee3 Check if subreg index is zero. 
llvm-svn: 88899
 2009-11-16 06:31:49 +00:00
Evan Cheng 11bf4493d4 For some targets, a copy can use a register multiple times, e.g. ppc. 
llvm-svn: 88895
 2009-11-16 05:52:06 +00:00
Evan Cheng 8ca5d4b9ad xfail for now. It has been failing. 
llvm-svn: 88892
 2009-11-16 05:44:04 +00:00
Bruno Cardoso Lopes 537e409c58 - Fix a small bug while handling target constant pools (one param was missing). 
- Add a smarter constant pool loading, instead of:

lui $2, %hi($CPI1_0)
addiu $2, $2, %lo($CPI1_0)
lwc1 $f0, 0($2)

Generate:

lui $2, %hi($CPI1_0)
lwc1 $f0, %lo($CPI1_0)($2)

llvm-svn: 88886
 2009-11-16 04:33:42 +00:00
Jim Grosbach 01c1cae34d Detect need for autoalignment of the stack earlier to catch spills more 
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

llvm-svn: 88874
 2009-11-15 21:45:34 +00:00
Jim Grosbach f16a3b7a9f remove xfail 
llvm-svn: 88817
 2009-11-14 21:57:35 +00:00
Richard Osborne d5f2745965 Add XCore support for arbitrary-sized aggregate returns. 
llvm-svn: 88802
 2009-11-14 19:33:35 +00:00
Evan Cheng 16797a1f55 Added getSubRegIndex(A,B) that returns subreg index of A to B. Use it to replace broken code in VirtRegRewriter. 
llvm-svn: 88753
 2009-11-14 03:42:17 +00:00
Evan Cheng 6ad7da96fe - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.

llvm-svn: 88745
 2009-11-14 02:55:43 +00:00
Evan Cheng e3b312fec9 Add radar number. 
llvm-svn: 88739
 2009-11-14 02:11:32 +00:00
Evan Cheng d2c10508cd Fix PR5412: Fix an inverted check and another missing sub-register check. 
llvm-svn: 88738
 2009-11-14 02:09:09 +00:00
Dan Gohman a627e26d39 Enable the tail call optimization when the caller returns undef. 
llvm-svn: 88737
 2009-11-14 02:06:30 +00:00
Evan Cheng 66401c90da When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
llvm-svn: 88734
 2009-11-14 01:50:00 +00:00
Evan Cheng 78fa302e7d Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers. 
llvm-svn: 88719
 2009-11-13 23:16:41 +00:00
Dan Gohman 225fa59cac When optimizing for size, don't tail-merge unless it's likely to be a 
code-size win, and not when it's only likely to be code-size neutral,
such as when only a single instruction would be eliminated and a new
branch would be required.

This fixes rdar://7392894.

llvm-svn: 88692
 2009-11-13 21:02:15 +00:00
Evan Cheng d190b8216f Fix PR5410: LiveVariables lost subreg def: 
D0<def,dead> = ...
...
             = S0<use, kill>
S0<def>      = ...
...
D0<def>      = 

The first D0 def is correctly marked dead, however, livevariables should have
added an implicit def of S0 or we end up with a use without a def.

llvm-svn: 88690
 2009-11-13 20:36:40 +00:00
Dan Gohman f80dc08059 Don't let a noalias difference disrupt the tailcall optimization. 
llvm-svn: 88672
 2009-11-13 18:49:38 +00:00
Dale Johannesen 5f4eecf961 Adjust isConstantSplat to allow for big-endian targets. 
PPC is such a target; make it work.

llvm-svn: 87060
 2009-11-13 01:45:18 +00:00
Daniel Dunbar 3f75f5ddcb Update test. 
llvm-svn: 87049
 2009-11-13 01:01:58 +00:00
Jim Grosbach 1025a4998b Clean up testcase a bit. Simplify case blocks and adjust switch instruction to not take an undefined value as input. 
llvm-svn: 86997
 2009-11-12 17:19:09 +00:00
Benjamin Kramer 5218176bc6 Fix typo in run line. 
llvm-svn: 86984
 2009-11-12 12:35:27 +00:00
Evan Cheng 5d85a46f76 RegScavenger::enterBasicBlock should always reset register state. 
llvm-svn: 86972
 2009-11-12 07:49:10 +00:00
Evan Cheng 85a9f430e9 - Teach LSR to avoid changing cmp iv stride if it will create an immediate that 
cannot be folded into target cmp instruction.
- Avoid a phase ordering issue where early cmp optimization would prevent the
  later count-to-zero optimization.
- Add missing checks which could cause LSR to reuse stride that does not have
  users.
- Fix a bug in count-to-zero optimization code which failed to find the pre-inc
  iv's phi node.
- Remove, tighten, loosen some incorrect checks disable valid transformations.
- Quite a bit of code clean up.

llvm-svn: 86969
 2009-11-12 07:35:05 +00:00
Dan Gohman 09478e975d Tail merge at any size when there are two potentials blocks and one 
can be made to fall through into the other.

llvm-svn: 86909
 2009-11-12 00:39:10 +00:00
Kenneth Uildriks 9f34406a90 x86 users can now return arbitrary sized structs. Structs too large to fit in return registers will be returned through a hidden sret parameter introduced during SelectionDAG construction. 
llvm-svn: 86876
 2009-11-11 19:59:24 +00:00
Dan Gohman 64b5d0f468 Add support for tail duplication to BranchFolding, and extend 
tail merging support to handle more cases.
 - Recognize several cases where tail merging is beneficial even when
   the tail size is smaller than the generic threshold.
 - Make use of MachineInstrDesc::isBarrier to help detect
   non-fallthrough blocks.
 - Check for and avoid disrupting fall-through edges in more cases.

llvm-svn: 86871
 2009-11-11 19:48:59 +00:00
Evan Cheng 7e5e40c75e Add nounwind. 
llvm-svn: 86814
 2009-11-11 07:11:02 +00:00
Bill Wendling d656f8ec4c Fix test to work on every platform. 
llvm-svn: 86786
 2009-11-11 01:44:22 +00:00
Bill Wendling 5831283cb5 Fix test to work on every platform. 
llvm-svn: 86785
 2009-11-11 01:41:32 +00:00
Bill Wendling 676f44062e Make sure that the exception handling data has the same visibility as the 
function it's generated for.

llvm-svn: 86779
 2009-11-11 01:24:59 +00:00
Bill Wendling 47739b20fd Test this on Darwin only. 
llvm-svn: 86752
 2009-11-10 23:18:33 +00:00
Dale Johannesen 6f7d5b22bb Emit correct code when making a ConstantPool entry for a vector 
constant whose component type is not a legal type for the target.
(If the target ConstantPool cannot handle this type either, it has
an opportunity to merge elements.  In practice any target with
8-bit bytes must support i8 *as data*).  7320806 (partial).

llvm-svn: 86751
 2009-11-10 23:16:41 +00:00
Bill Wendling fc9469f311 Modify how the prologue encoded the "move" information for the FDE. GCC 
generates a sequence similar to this:

__Z4funci:
LFB2:
        mflr r0
LCFI0:
        stmw r30,-8(r1)
LCFI1:
        stw r0,8(r1)
LCFI2:
        stwu r1,-80(r1)
LCFI3:
        mr r30,r1
LCFI4:

where LCFI3 and LCFI4 are used by the FDE to indicate what the FP, LR, and other
things are. We generated something more like this:

Leh_func_begin1:
        mflr r0
        stw r31, 20(r1)
        stw r0, 8(r1)
Llabel1:
        stwu r1, -80(r1)
Llabel2:
        mr r31, r1

Note that we are missing the "mr" instruction. This patch makes it more like the
GCC output.

llvm-svn: 86729
 2009-11-10 22:14:04 +00:00
Mike Stump f8a74fc4a5 Add testcase for recent checkin. 
llvm-svn: 86620
 2009-11-09 23:10:49 +00:00
Jim Grosbach 47e3bcf180 Update test 
llvm-svn: 86614
 2009-11-09 22:59:01 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Anton Korobeynikov 700c4ab3f9 Add and-not (bic) patterns. Based heavily on patch by Brian Lucas! 
llvm-svn: 86471
 2009-11-08 15:33:12 +00:00
Anton Korobeynikov 4ca8d3a6a6 Fix invalid operand updates & implement post-inc memory operands 
llvm-svn: 86466
 2009-11-08 14:27:38 +00:00
Anton Korobeynikov dc2beaa05e It is invalid to infer the value type from the result #0 of the node 
since the instruction might use the other result of different type.

llvm-svn: 86462
 2009-11-08 12:14:54 +00:00
Nate Begeman 3a313df69b x86 vector shuffle cleanup/fixes: 
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415
 2009-11-07 23:17:15 +00:00
Anton Korobeynikov d3c8319f48 Add some dummy support for post-incremented loads 
llvm-svn: 86385
 2009-11-07 17:15:06 +00:00
Anton Korobeynikov f93bb39b03 Add 8 bit libcalls and make use of them for msp430 
llvm-svn: 86384
 2009-11-07 17:14:39 +00:00
Anton Korobeynikov 2a88785685 Initial support for addrmode handling. Tests by Brian Lucas! 
llvm-svn: 86382
 2009-11-07 17:13:35 +00:00
Anton Korobeynikov 226467d6a6 It turns out that the testcase in question uncovered subreg-handling bug. 
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375
 2009-11-07 15:20:32 +00:00
Eric Christopher bd05185ef1 Fix a couple of shuffle patterns to use movhlps instead 
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360
 2009-11-07 08:45:53 +00:00
Chris Lattner 8e1d7222a7 Fix PR5421 by APInt'izing switch lowering. 
llvm-svn: 86354
 2009-11-07 07:50:34 +00:00
Chris Lattner 74ab6efbe8 merge cmp1 into cmp0 and filecheckize. 
llvm-svn: 86345
 2009-11-07 06:19:20 +00:00
Evan Cheng a8e8a7c976 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic. 
llvm-svn: 86330
 2009-11-07 04:04:34 +00:00
Evan Cheng 7ff831962a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical 
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328
 2009-11-07 03:52:02 +00:00
Evan Cheng 207b246650 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Anton Korobeynikov 9df3acf486 Honour subreg machine operands during asmprinting 
llvm-svn: 86303
 2009-11-06 23:45:15 +00:00
Bob Wilson d95ccd6c4d Print VMOV (immediate) operands as hexadecimal values. Apple's assembler 
will not accept negative values for these.  LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates.  Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.

llvm-svn: 86301
 2009-11-06 23:33:28 +00:00
Bob Wilson db42ca663b Fix a broken test. 
llvm-svn: 86298
 2009-11-06 23:06:42 +00:00
Evan Cheng 408aa56fb5 Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead. 
llvm-svn: 86294
 2009-11-06 22:24:13 +00:00
Eric Christopher 80f04dc67d Fix PR5315, original patch by Nicolas Capens! 
llvm-svn: 86203
 2009-11-06 00:11:57 +00:00
Dan Gohman 98693a3ac2 Update these tests for the new label names. 
llvm-svn: 86192
 2009-11-05 23:31:40 +00:00
Bob Wilson 45119d8850 Add -mtriple to llc commands, attempting to fix buildbot failures. 
llvm-svn: 86086
 2009-11-05 00:51:31 +00:00
Bob Wilson 90d0b82e12 Attempt again to fix buildbot failures: make expected output less specific 
and compile with -mtriple to specify *-apple-darwin targets.

llvm-svn: 86081
 2009-11-05 00:30:35 +00:00
Bob Wilson f84f7105f7 Add PowerPC codegen for indirect branches. 
llvm-svn: 86050
 2009-11-04 21:31:18 +00:00
Bob Wilson e8ca96cf24 Fix broken test. 
llvm-svn: 86045
 2009-11-04 20:04:11 +00:00
Bob Wilson 16f60b9216 Add test for ARM indirectbr codegen. 
llvm-svn: 86042
 2009-11-04 19:25:34 +00:00
Evan Cheng 95bdc5d899 RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg, 
and extract_subreg as a "copy" that defines a valno.
Also fixes a typo. These two issues prevent a simple subreg coalescing from
happening before.

llvm-svn: 86022
 2009-11-04 08:33:14 +00:00
Evan Cheng 8f4e3d99c9 Fix test. 
llvm-svn: 85986
 2009-11-04 00:42:33 +00:00
Evan Cheng 0410bced1c fconsts / fconstd immediate should be proceeded with #. 
llvm-svn: 85952
 2009-11-03 21:59:33 +00:00
Evan Cheng f42b5af549 Re-apply 85799. It turns out my code isn't buggy. 
llvm-svn: 85947
 2009-11-03 21:40:02 +00:00
Kenneth Uildriks 90fedc6ef9 Make opt default to not adding a target data string and update tests that depend on target data to supply it within the test 
llvm-svn: 85900
 2009-11-03 15:29:06 +00:00
Evan Cheng 8d681f0471 Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. 
llvm-svn: 85871
 2009-11-03 05:52:54 +00:00
Nate Begeman a21bc75d78 Declare sin & cos as readonly so they match the code in SelectionDAGBuild 
llvm-svn: 85853
 2009-11-03 02:19:31 +00:00
Anton Korobeynikov 2c2dc9f64f Temporary xfail until PR5367 will be resolved 
llvm-svn: 85848
 2009-11-03 00:37:36 +00:00
Anton Korobeynikov fbe0256b23 Revert r85049, it is causing PR5367 
llvm-svn: 85847
 2009-11-03 00:24:48 +00:00
Evan Cheng a8a58efc03 Revert 85799 for now. It might be breaking llvm-gcc driver. 
llvm-svn: 85827
 2009-11-02 21:49:14 +00:00
Evan Cheng 2729543984 Initilize the machine LICM CSE map upon the first time an instruction is hoisted to 
the loop preheader. Add instructions which are already in the preheader block that
may be common expressions of those that are hoisted out. These does get a few more
instructions CSE'ed.

llvm-svn: 85799
 2009-11-02 08:09:49 +00:00
Evan Cheng fb2d385221 Remove an irrelevant and poorly reduced test case. 
llvm-svn: 85794
 2009-11-02 07:11:54 +00:00
Evan Cheng 1708b06c0e Unbreak ARMBaseRegisterInfo::copyRegToReg. 
llvm-svn: 85787
 2009-11-02 04:44:55 +00:00
Anton Korobeynikov 4d23754b14 Handle splats of undefs properly. This includes the testcase for PR5364 as well. 
llvm-svn: 85767
 2009-11-02 00:12:06 +00:00
Anton Korobeynikov 8cce1eb6aa 64-bit FP loads & stores operate on both NEON and VFP pipelines. 
llvm-svn: 85765
 2009-11-02 00:11:06 +00:00
Evan Cheng 43219997b6 Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. 
llvm-svn: 85743
 2009-11-01 21:12:51 +00:00
Evan Cheng 50bc004b67 Fix tests. 
llvm-svn: 85723
 2009-11-01 18:13:29 +00:00
Chris Lattner 50ba5c3dc2 improve x86 codegen support for blockaddress. We now compile 
the testcase into:

_test1:                                                     ## @test1
## BB#0:                                                    ## %entry
	leaq	L_test1_bb6(%rip), %rax
	jmpq	*%rax
L_test1_bb:                                                 ## Address Taken
LBB1_1:                                                     ## %bb
	movb	$1, %al
	ret
L_test1_bb6:                                                ## Address Taken
LBB1_2:                                                     ## %bb6
	movb	$2, %al
	ret

Note, it is very very strange that BlockAddressSDNode doesn't carry 
around TargetFlags.  Dan, please fix this.

llvm-svn: 85703
 2009-11-01 03:25:03 +00:00
Evan Cheng 6f29ad9170 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Jim Grosbach 5cba8de2c8 vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid using 
them for scalar floating point operations for now.

llvm-svn: 85697
 2009-10-31 22:57:36 +00:00
Jim Grosbach 403202aef1 Consolidate test files 
llvm-svn: 85696
 2009-10-31 22:20:56 +00:00
Jim Grosbach c79fb530d4 Change to use FileCheck 
llvm-svn: 85695
 2009-10-31 22:16:14 +00:00
Jim Grosbach 69f364babc Make tests more explicit about which instructions are expected. 
llvm-svn: 85694
 2009-10-31 22:14:17 +00:00
Jim Grosbach 259c37cc55 Grammar tweak to comments 
llvm-svn: 85693
 2009-10-31 22:12:44 +00:00
Jim Grosbach 2c3e618a06 Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85691
 2009-10-31 22:10:38 +00:00
Jim Grosbach 0de95af62d Update test to be more explicit about what instruction sequences are expected for each operation. 
llvm-svn: 85689
 2009-10-31 21:52:58 +00:00
Jim Grosbach 8fe6fd702d Expand 64-bit logical shift right inline 
llvm-svn: 85687
 2009-10-31 21:42:19 +00:00
Jim Grosbach 624fcb286e Expand 64-bit arithmetic shift right inline 
llvm-svn: 85685
 2009-10-31 21:00:56 +00:00
Benjamin Kramer 6ef6fe1c31 Force triple; darwin's ASM syntax differs from linux's. 
llvm-svn: 85676
 2009-10-31 19:54:06 +00:00