3 Commits

Author	SHA1	Message	Date
Alex Bradbury	6b2cca7f8f	[RISCV] Add bare-bones RISC-V MCTargetDesc ... This is enough to compile and link but doesn't yet do anything particularly useful. Once an ASM parser and printer are added in the next two patches, the whole thing can be usefully tested. Differential Revision: https://reviews.llvm.org/D23562 llvm-svn: 285770	2016-11-01 23:47:30 +00:00
Alex Bradbury	24d9b13b36	[RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td ... For now, only add instruction definitions for basic ALU operations. Our initial target is a working MC layer rather than codegen, so appropriate SelectionDAG patterns will come later. Differential Revision: https://reviews.llvm.org/D23561 llvm-svn: 285769	2016-11-01 23:40:28 +00:00
Alex Bradbury	b2e5472d85	[RISCV] Add stub backend ... This contains just enough for lib/Target/RISCV to compile. Notably a basic RISCVTargetMachine and RISCVTargetInfo. At this point you can attempt llc -march=riscv32 myinput.ll and will find it fails due to the lack of MCAsmInfo. See http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html for further discussion Differential Revision: https://reviews.llvm.org/D23560 llvm-svn: 285712	2016-11-01 17:27:54 +00:00