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1408 Commits

Author SHA1 Message Date
Evan Cheng d4d352c663 80 column violation. 
llvm-svn: 78657
 2009-08-11 08:47:46 +00:00
Evan Cheng 192d7c0752 Cosmetic changes. 
llvm-svn: 78655
 2009-08-11 07:36:14 +00:00
Evan Cheng 6e62e93a8d Adding a blank line back. 
llvm-svn: 78654
 2009-08-11 07:32:58 +00:00
Bob Wilson 12842f9865 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Bob Wilson 741a9c7bf6 Use new EVT::vAny type to combine Neon intrinsics for VPADD. 
llvm-svn: 78632
 2009-08-11 01:15:26 +00:00
David Goodwin b80734bb15 Fix bug in NEON convert for single-precision FP. This also fixes the tblgen warnings. 
llvm-svn: 78629
 2009-08-11 01:07:38 +00:00
Jim Grosbach 9382d5ac05 Add stdlib.h 
llvm-svn: 78627
 2009-08-11 00:20:00 +00:00
Jim Grosbach 693e36a3e8 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
 2009-08-11 00:09:57 +00:00
Evan Cheng 475f8a4fa2 Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck. 
llvm-svn: 78622
 2009-08-10 23:56:04 +00:00
Dan Gohman 733a64db57 Fix a bug where DAGCombine was producing an illegal ConstantFP 
node after legalize, and remove the workaround code from the
ARM backend.

llvm-svn: 78615
 2009-08-10 23:15:10 +00:00
Owen Anderson 53aa7a960c Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
David Goodwin 85b5b027f7 Use NEON for single-precision int<->FP conversions. 
llvm-svn: 78604
 2009-08-10 22:17:39 +00:00
Owen Anderson 3e77df2bcd SimpleValueType-ify a few more methods on TargetLowering. 
llvm-svn: 78595
 2009-08-10 20:46:15 +00:00
Evan Cheng f72c13bdf5 Handle the constantfp created during post-legalization dag combiner phase. 
llvm-svn: 78594
 2009-08-10 20:25:59 +00:00
Owen Anderson 246617857f Continue the SimpleValueType-ification. 
llvm-svn: 78593
 2009-08-10 20:18:46 +00:00
Chris Lattner 6c20391d38 split MachO section handling stuff out to its out .h/.cpp file. 
llvm-svn: 78576
 2009-08-10 18:15:01 +00:00
Chris Lattner fbcafd4c6c arm only needs to emit one .align directive for hidden nlp's, not one 
per pointer.

llvm-svn: 78574
 2009-08-10 18:02:16 +00:00
Chris Lattner 292472d3d3 make sure that arm nonlazypointers are aligned properly 
llvm-svn: 78573
 2009-08-10 18:01:34 +00:00
David Goodwin 62e053b790 Checkpoint scheduling itinerary changes. 
llvm-svn: 78564
 2009-08-10 15:56:13 +00:00
Evan Cheng 5bb93ce769 Watch out for empty BB. 
llvm-svn: 78562
 2009-08-10 08:10:13 +00:00
Evan Cheng 8a640ae504 rev, rev16, and revsh do not set CPSR. 
llvm-svn: 78561
 2009-08-10 07:58:45 +00:00
Evan Cheng f16a1d5b79 Duh. Most 16-bit Thumb rr instructions are two-address. Fix table. 
llvm-svn: 78560
 2009-08-10 07:20:37 +00:00
Evan Cheng 1f5bee14a1 CPSR can be livein; transfer predicate operands correctly; tMUL is two-address. 
llvm-svn: 78559
 2009-08-10 06:57:42 +00:00
Evan Cheng 092b701a2c Add support for folding loads / stores into 16-bit moves used by Thumb2. 
llvm-svn: 78558
 2009-08-10 06:32:05 +00:00
Evan Cheng 55c014a9f3 80 col violation. 
llvm-svn: 78557
 2009-08-10 05:51:48 +00:00
Evan Cheng f5b73869f2 Use tMOVgpr2gpr instead of t2MOVr. 
llvm-svn: 78556
 2009-08-10 05:49:43 +00:00
Evan Cheng 51cbd2d6c4 Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Evan Cheng 5b4c308f0c Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr. 
llvm-svn: 78549
 2009-08-10 02:06:53 +00:00
Chris Lattner cb307a27bf Make the big switch: Change MCSectionMachO to represent a section *semantically* 
instead of syntactically as a string.  This means that it keeps track of the 
segment, section, flags, etc directly and asmprints them in the right format.
This also includes parsing and validation support for llvm-mc and 
"attribute(section)", so we should now start getting errors about invalid 
section attributes from the compiler instead of the assembler on darwin.

Still todo: 
1) Uniquing of darwin mcsections
2) Move all the Darwin stuff out to MCSectionMachO.[cpp|h]
3) there are a few FIXMEs, for example what is the syntax to get the
   S_GB_ZEROFILL segment type?

llvm-svn: 78547
 2009-08-10 01:39:42 +00:00
Evan Cheng d461c1c559 Add support to convert 32-bit instructions to 16-bit non-two-address ones. 
llvm-svn: 78540
 2009-08-09 19:17:19 +00:00
Anton Korobeynikov cfed3005e5 Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Chris Lattner 1cb9396f4f 1. Make MCSection an abstract class. 
2. Move section switch printing to MCSection virtual method which takes a
   TAI.  This eliminates textual formatting stuff from TLOF.
3. Eliminate SwitchToSectionDirective, getSectionFlagsAsString, and 
   TLOFELF::AtIsCommentChar.

llvm-svn: 78510
 2009-08-08 22:41:53 +00:00
Chris Lattner ce7d14032b now that getOrCreateSection is all object-file specific, 
give the impls an object-file-specific name.  In the future
they can take different arguments etc.

llvm-svn: 78495
 2009-08-08 20:22:20 +00:00
Daniel Dunbar 028f6dc4c2 Update CMake 
llvm-svn: 78475
 2009-08-08 17:03:13 +00:00
Anton Korobeynikov 7167f33872 Add insert_elt / extract_elt patterns for v4f32 stuff. 
Did anyone tests v4f32 ever?

llvm-svn: 78470
 2009-08-08 14:06:07 +00:00
Anton Korobeynikov 4218516f5d Lane number should be printed w/o hash 
llvm-svn: 78469
 2009-08-08 14:05:53 +00:00
Anton Korobeynikov 887d05ce9b Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
Bob Wilson e2231070ff Implement Neon VZIP and VUZP instructions. These are very similar to VTRN, 
so I generalized the class for VTRN in the .td file to handle all 3 of them.

llvm-svn: 78460
 2009-08-08 06:13:25 +00:00
Bob Wilson db46af0461 Implement Neon VTRN instructions. For now, anyway, these are selected 
directly from the intrinsics produced by the frontend.  If it is more
convenient to have a custom DAG node for using these to implement shuffles,
we can add that later.

llvm-svn: 78459
 2009-08-08 05:53:00 +00:00
Evan Cheng 1be453b462 Add a skeleton Thumb2 instruction size reduction pass. 
llvm-svn: 78456
 2009-08-08 03:21:23 +00:00
Evan Cheng 2aa91cc2be Code refactoring. No functionality change. 
llvm-svn: 78455
 2009-08-08 03:20:32 +00:00
Evan Cheng 274fcbe43e tADDhirr should target GPR, not tGPR. 
llvm-svn: 78454
 2009-08-08 03:19:44 +00:00
Evan Cheng 4dc201eb64 I can type. 
llvm-svn: 78453
 2009-08-08 02:54:37 +00:00
Chris Lattner b94284b5e2 make printInstruction return void since its result is omitted. Make the 
error condition get trapped with an assert.

llvm-svn: 78449
 2009-08-08 01:32:19 +00:00
David Goodwin 742db6a6d4 Make NEON single-precision FP support the default for cortex-a8 (again). 
llvm-svn: 78430
 2009-08-07 23:32:33 +00:00
Anton Korobeynikov d28a26dfab Unbreak the stuff 
llvm-svn: 78425
 2009-08-07 22:51:13 +00:00
Anton Korobeynikov 23b28cb824 2 more vdup.32 cases 
llvm-svn: 78419
 2009-08-07 22:36:50 +00:00
Evan Cheng fb93be2b6f A big oops. Thumb1 default CC is a def of CPSR, not a use of CPSR. 
llvm-svn: 78418
 2009-08-07 22:36:37 +00:00
Evan Cheng 6e130db3b7 Thumb2 32-bit ldm / stm needs .w suffix if submode is ia. 
llvm-svn: 78410
 2009-08-07 21:19:10 +00:00
Evan Cheng b64ec07ea6 This is done. 
llvm-svn: 78399
 2009-08-07 19:34:52 +00:00