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5 Commits

Author SHA1 Message Date
Jacques Pienaar c3a162c451 [lanai] Add more tests for assembly of conditional ALU ops 
llvm-svn: 275081
 2016-07-11 17:58:16 +00:00
Jacques Pienaar b32a912f72 [lanai] Treat .t as optional in assembly parser for RR operands and add predicate operand to ShiftRR 
llvm-svn: 274980
 2016-07-09 18:26:04 +00:00
Jacques Pienaar 6d3eecc843 [lanai] Use peephole optimizer to generate more conditional ALU operations. 
Summary:
* Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations;
* Add predicated type with default always true to RR instructions in LanaiInstrInfo.td;
* Move LanaiSetflagAluCombiner into optimizeCompare;
* The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test;
* Remove unused MachineOperand flags;

Reviewers: eliben

Subscribers: aemerson

Differential Revision: http://reviews.llvm.org/D22072

llvm-svn: 274807
 2016-07-07 23:36:04 +00:00
Jacques Pienaar 4badd6aaf3 [lanai] isBrImm should accept any non-constant immediate. 
isBrImm should accept any non-constant immediate. Previously it was only accepting LanaiMCExpr ones which was wrong.

Differential Revision: http://reviews.llvm.org/D18571

llvm-svn: 265032
 2016-03-31 17:58:55 +00:00
Jacques Pienaar fcef3e4617 [lanai] Add Lanai backend. 
Add the Lanai backend to lib/Target.

General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend" (http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html).

Differential Revision: http://reviews.llvm.org/D17011

llvm-svn: 264578
 2016-03-28 13:09:54 +00:00