e480ed0b9f
[X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256
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These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents.
Differential Revision: https://reviews.llvm.org/D46229
llvm-svn: 331659
2018-05-07 18:25:19 +00:00
ac5d0a31ef
[X86] Split WriteFDiv schedule classes to support single/double scalar, XMM and YMM/ZMM instructions.
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This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values.
llvm-svn: 331643
2018-05-07 16:15:46 +00:00
f3ae50fca2
[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classes
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WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions.
WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions.
This removes all InstrRW overrides for these instructions.
NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner.
NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80.
llvm-svn: 331629
2018-05-07 11:50:44 +00:00
0e51a125ea
[X86] Add WriteEMMS scheduler class
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Filled in the missing values from Btver2 SoG or Agner
llvm-svn: 331546
2018-05-04 18:16:13 +00:00
d7ffbc5c7e
[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
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llvm-svn: 331543
2018-05-04 17:47:46 +00:00
67cc246dca
[X86] Cleanup SchedWriteFMA classes and use X86SchedWriteWidths directly.
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Rename scalar and XMM versions, this is to match/simplify an upcoming change to split MUL/DIV/SQRT scalar/xmm/ymm/zmm classes.
llvm-svn: 331531
2018-05-04 15:20:18 +00:00
bf4c8c0ff2
[X86] Add WriteVecMOVMSKY scheduler class
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llvm-svn: 331525
2018-05-04 14:54:33 +00:00
be51b20127
[X86] Add SchedWriteFRnd fp rounding scheduler classes
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Split off from SchedWriteFAdd for fp rounding/bit-manipulation instructions.
Fixes an issue on btver2 which only had the ymm version using the JSTC pipe instead of JFPA.
llvm-svn: 331515
2018-05-04 12:59:24 +00:00
542b20d656
[X86] Add WriteDPPD/WriteDPPS dot product scheduler classes
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llvm-svn: 331489
2018-05-03 22:31:19 +00:00
0720c8d90e
[X86][AVX512] VPLZCNT instructions match SchedWriteVecIMul scheduling class not SchedWriteVecALU.
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llvm-svn: 331473
2018-05-03 18:22:49 +00:00
f2d2cedab4
[X86] Split WriteVecShift/WriteVarVecShift into MMX, XMM and YMM/ZMM scheduler classes
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This took a bit of extra work as on Intel targets the old (V)PSLLDrr/(V)PSLLDrm style instructions act differently - I ended up creating WriteVecShiftImm classes for XMM/YMM/ZMM vector shift by immediate and retaining WriteVecShift as the default (used only by MMX) plus WriteVecShiftX/WriteVecShiftY. X86SchedWriteWidths hides most of this thank goodness.
llvm-svn: 331472
2018-05-03 17:56:43 +00:00
f7dd6069a5
[X86] Split WriteVecALU/WritePHAdd into XMM and YMM/ZMM scheduler classes
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llvm-svn: 331453
2018-05-03 13:27:10 +00:00
93c878c76b
[X86] Split WriteVecIMul/WriteVecPMULLD/WriteMPSAD/WritePSADBW into XMM and YMM/ZMM scheduler classes
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Also retagged VDBPSADBW instructions as SchedWritePSADBW instead of SchedWriteVecIMul which matches the behaviour on SkylakeServer (the only thing that supports it...)
llvm-svn: 331445
2018-05-03 10:31:20 +00:00
6732f6ea51
[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
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llvm-svn: 331386
2018-05-02 18:48:23 +00:00
819f218f07
[X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
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llvm-svn: 331380
2018-05-02 17:58:50 +00:00
e93fd5f1e4
[X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values
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Intel models were targeting x87 instead of packed sse.
Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.
llvm-svn: 331340
2018-05-02 09:18:49 +00:00
21caf0124f
[X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classes
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llvm-svn: 331293
2018-05-01 18:22:53 +00:00
c708868cb1
[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and YMM/ZMM scheduler classes
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llvm-svn: 331290
2018-05-01 18:06:07 +00:00
c546f9424f
[X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classes
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Removes more WriteFCmp InstRW overrides
llvm-svn: 331283
2018-05-01 16:50:16 +00:00
5269167f5b
[X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes
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Removes more WriteFAdd InstRW overrides
llvm-svn: 331276
2018-05-01 16:13:42 +00:00
dd8eae128b
[X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes
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Removes more WriteFShuffle InstRW overrides
llvm-svn: 331264
2018-05-01 14:25:01 +00:00
57f2b185ac
[X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes
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This removes all the WriteVecLogic InstRW overrides.
llvm-svn: 331258
2018-05-01 12:39:17 +00:00
fc0c26f1a6
[X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
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Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.
llvm-svn: 331253
2018-05-01 11:05:42 +00:00
0a732da261
[X86] Drop unnecessary VPORrm InstrRW override in SkylakeServer.
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llvm-svn: 331188
2018-04-30 15:18:33 +00:00
b521ec7525
[X86] Fix SkylakeServer typo in WritePSADBW class - it only uses 1 resource.
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llvm-svn: 331187
2018-04-30 15:17:16 +00:00
318f816f49
[X86] Fix typo in skylake-avx512 model for PMAXSD/PMINSD instructions
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The PMAXSD/PMINSD instregexs had been written as PMAX(C?)SD - looks like this was a search+replace error when matching float MAXSD/MINSD commutative instructions.
llvm-svn: 331167
2018-04-30 10:46:35 +00:00
d5ada498db
[X86] Merge more instregex single matches to reduce InstrRW compile time.
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llvm-svn: 331143
2018-04-29 15:33:15 +00:00
ebd3e4a69c
[X86] Remove SLDT64m instruction.
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It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.
While I was touching the encoding tests to remove it, I added some other missing register form test cases.
llvm-svn: 331135
2018-04-29 04:50:53 +00:00
39d7720354
[X86] Remove unnecessary shift/rotate folded InstRW overrides.
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llvm-svn: 331110
2018-04-28 15:32:19 +00:00
8ee7d01dcf
[X86] Merge some x87 instruction instregex single matches. NFCI.
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llvm-svn: 331084
2018-04-27 21:14:19 +00:00
8a937e00d8
[X86] Split WriteFBlend/WriteFVarBlend/WriteFVarShuffle into XMM and YMM/ZMM scheduler classes
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This removes all the WriteFBlend/WriteFVarBlend InstRW overrides - some WriteFVarShuffle remain to be fixed.
llvm-svn: 331065
2018-04-27 18:19:48 +00:00
c3c767bf50
[X86] Split WriteFHadd into XMM and YMM/ZMM scheduler classes
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This removes all the HADD/HSUB PS/PD InstRW overrides.
llvm-svn: 331054
2018-04-27 16:11:57 +00:00
b2aa89c909
[X86][AVX] Split WriteFLogic into XMM and YMM/ZMM scheduler classes
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This removes all the AND/ANDN/OR/XOR PS/PD InstRW overrides.
llvm-svn: 331051
2018-04-27 15:50:33 +00:00
aef5ca7299
[X86] Replace some system instruction instregex single matches with instrs entry. NFCI.
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llvm-svn: 331034
2018-04-27 13:32:42 +00:00
dbd1ae7ddd
[X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classes
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This removes all the FMA InstRW overrides.
If we ever get PR36924, then we can remove many of these declarations from models.
llvm-svn: 330820
2018-04-25 13:07:58 +00:00
6a82e96ed9
[X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.
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llvm-svn: 330813
2018-04-25 10:51:19 +00:00
c4d25a2922
[X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.
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llvm-svn: 330760
2018-04-24 19:22:01 +00:00
27bc83e228
[X86] Split off PHMINPOSUW to their own schedule class
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This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default.
llvm-svn: 330756
2018-04-24 18:49:25 +00:00
f0945aa0e0
[X86][F16C] Add WriteCvtF2FSt scheduling class
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Fixes the classification of VCVTPS2PHmr/VCVTPS2PHYmr which were tagged as WriteCvtF2FLd_WriteRMW (PR36887)
llvm-svn: 330737
2018-04-24 16:43:07 +00:00
16299273d0
[X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides.
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llvm-svn: 330720
2018-04-24 14:47:11 +00:00
f7d2a93d5f
[X86] Add vector element insertion/extraction scheduler classes
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Split off pinsr/pextr and extractps instructions.
(Mostly) fixes PR36887.
Note: It might be worth adding a WriteFInsertLd class as well in the future.
Differential Revision: https://reviews.llvm.org/D45929
llvm-svn: 330714
2018-04-24 13:21:41 +00:00
e5e4bf02d6
[X86] Remove unnecessary vector memory folded InstRW overrides.
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We have test coverage for these with resources-sse*/avx*
llvm-svn: 330662
2018-04-23 22:45:04 +00:00
eb6090941c
[X86] Remove unnecessary BMI2 InstRW overrides.
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We have test coverage for these with resources-bmi2.s
llvm-svn: 330659
2018-04-23 22:19:55 +00:00
ed09ebb48d
[X86] Remove unnecessary WriteLEA InstRW overrides.
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llvm-svn: 330648
2018-04-23 21:04:23 +00:00
8cd01aaa0f
[X86] Replace x87 instregex with instrs if they only match one instruction
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llvm-svn: 330611
2018-04-23 16:10:50 +00:00
455d0b2cfe
[X86] Remove instregex matching from CLAC/STAC.
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Note - noticed this as the STAC case as it was unintentionally matching against *STACK* pseudo instructions.
llvm-svn: 330588
2018-04-23 13:24:17 +00:00
0a334a8668
[X86] Remove unnecessary MMX reg-mem InstRW scheduler overrides.
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llvm-svn: 330581
2018-04-23 11:57:15 +00:00
06e16541ba
[X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides.
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Fixed a lot of the default classes which were being completely overridden.
llvm-svn: 330554
2018-04-22 18:35:53 +00:00
091680b6e7
[X86] Remove unnecessary WriteFMul/WriteFRcp/WriteFRsqrt InstRW overrides.
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llvm-svn: 330553
2018-04-22 18:09:50 +00:00
c7f9b183c2
[X86][SkylakeServer] Remove unnecessary PMULLD instrw overrides.
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llvm-svn: 330549
2018-04-22 16:51:12 +00:00
Simon Pilgrim