c3b0427921
Allow MCCodeEmitter access to the target MCRegisterInfo.
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Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
llvm-svn: 156828
2012-05-15 17:35:52 +00:00
9f7ad310b5
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
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the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.
rdar://11318438
llvm-svn: 155601
2012-04-26 01:13:36 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
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llvm-svn: 147115
2011-12-22 00:37:50 +00:00
5928e69d20
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
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llvm-svn: 136010
2011-07-25 23:24:55 +00:00
287bc6bdf6
ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable.
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llvm-svn: 135837
2011-07-23 01:16:22 +00:00
ad5f485957
Sink ARM mc routines into MCTargetDesc.
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llvm-svn: 135825
2011-07-23 00:00:19 +00:00
bc153d49b7
Next round of MC refactoring. This patch factor MC table instantiations, MC
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
2011-07-14 20:59:42 +00:00
4d1ca96bfc
Eliminate asm parser's dependency on TargetMachine:
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- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
llvm-svn: 134678
2011-07-08 01:53:10 +00:00
f2c2616e72
Sink feature IsThumb into MC layer.
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llvm-svn: 134608
2011-07-07 08:26:46 +00:00
2bd65363a8
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
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llvm-svn: 134569
2011-07-07 00:08:19 +00:00
928ce72bcd
Add ARM MC registry routines.
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llvm-svn: 134547
2011-07-06 22:02:34 +00:00
Jim Grosbach