Commit Graph

413135 Commits

Author SHA1 Message Date
Shoaib Meenai f4744e9ae0 Reapply "[llvm-libtool-darwin] Print a warning if object file names are repeated"
Loosen the test to make it pass on Windows.

This reapplies commit 4993eff3e2.
This reverts commit 96c6604012.
2022-01-28 10:19:33 -08:00
Stella Stamenova 738d73fbf4 [lldb] Update the lldb build instructions on Windows
The existing instructions for lldb on Windows can be more explicit. This adds a few details on how to install various components and the easiest way to get to a working build.

Reviewed By: JDevlieghere

Differential Revision: https://reviews.llvm.org/D118425
2022-01-28 10:18:19 -08:00
Shubham Sandeep Rastogi 4ce1f3d47c Emit swift5 reflection section data in dsym bundle generated by dsymutil in the Dwarf section.
Add support for Swift reflection metadata to dsymutil.

This patch adds support for copying Swift reflection metadata (__swift5_.* sections) from .o files to into the symbol-rich binary in the output .dSYM. The functionality is automatically enabled only if a .o file has reflection metadata sections and the binary doesn't. When copying dsymutil moves the section from the __TEXT segment to the __DWARF segment.

rdar://76973336

Differential Revision: https://reviews.llvm.org/D115007
2022-01-28 10:13:17 -08:00
Stella Stamenova c0861fcbb9 [mlir] Only build mlir-cpu-runner when the native arch is targeted
mlir-cpu-runner has a dependency on ExecutionEngine which is only built for the native arch. So currently mlir-cpu-runner does not link correctly when the native arch is not targeted.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D118422
2022-01-28 10:09:09 -08:00
Yuanfang Chen a41c8b8fd5 [ADT] support fixed-width output with `utohexstr`
Will use it to output a hash value that needs fixed-width.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D118427
2022-01-28 10:07:54 -08:00
Jay Foad 68e3946270 [AMDGPU] SILoadStoreOptimizer: break lists on instructions with side effects
This just helps to keep the lists shorter and faster to sort. NFCI.

Differential Revision: https://reviews.llvm.org/D118384
2022-01-28 18:03:42 +00:00
Craig Topper 06bd56d47d [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
After D118175, we get the information from the tablegen definition.

Differential Revision: https://reviews.llvm.org/D118488
2022-01-28 09:51:49 -08:00
Steven Wan 760e69223d [NFC][AIX]Disable new pcm tests on AIX
Same as D114481, the PCH reader looks for a `__clangast` section in the precompiled module file, which isn't present on AIX, and we don't support writing this custom section in XCOFF yet.

Reviewed By: Jake-Egan, daltenty, sfertile

Differential Revision: https://reviews.llvm.org/D118477
2022-01-28 12:39:09 -05:00
Craig Topper ea05ee9059 [RISCV] Preserve VL when truncating i64 gather/scatter indices on RV32.
We were creating a truncate with the default for the type, but for
VP intrinsics we have a VL that we should use.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D118406
2022-01-28 09:25:30 -08:00
Ellis Hoag eea002a9c4 [InstrProf][NFC] Move function out of InstrProf.h
`createIRLevelProfileFlagVar()` seems to be only used in
`PGOInstrumentation.cpp` so we move it to that file. Then it can also
take advantage of directly using options rather than passing them as
arguments.

Reviewed By: kyulee, phosek

Differential Revision: https://reviews.llvm.org/D118097
2022-01-28 09:24:26 -08:00
Craig Topper de0c2d75bf [RISCV] Use tablegen size for getInstSizeInBytes.
Fix the pseudos to have the correct size in the MCInstrDesc description.

Inspired by D118009 and D117970.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118175
2022-01-28 09:21:28 -08:00
Alexey Bataev cec8b614f3 [SLP]Do not reorder top nodes if they do not require reordering.
No need to reorder the top nodes, if they are not stores or
insertelement instructions and each node should be analized only
once, when the bottom-to-top analysis is performed.
We still endup with extractelements for the top node scalars and
the final shuffle just adds an extra cost and currently
crashes the compiler for PHI nodes.

Differential Revision: https://reviews.llvm.org/D116760
2022-01-28 09:16:18 -08:00
Fangrui Song c80d349859 [msan][tsan] Refine __fxstat{,at}{,64} condition
In glibc before 2.33, include/sys/stat.h defines fstat/fstat64 to
`__fxstat/__fxstat64` and provides `__fxstat/__fxstat64` in libc_nonshared.a.
The symbols are glibc specific and not needed on other systems.

Reviewed By: vitalybuka, #sanitizers

Differential Revision: https://reviews.llvm.org/D118423
2022-01-28 09:15:39 -08:00
Cullen Rhodes 5d089d9a83 [DAGCombiner] Fix invalid size request in combineRepeatedFPDivisors
If we have a vector FP division with a splatted divisor, use
getVectorMinNumElements when scaling the num of uses by splat factor.

For AArch64 the combine kicks in for the <vscale x 4 x float> case since it's
above the fdiv threshold (3) when scaling num uses by splat factor, but the
codegen is worse (splat + vector fdiv + vector fmul) than the <vscale x 2 x
double> case (splat + vector fdiv).

If the combine could be converted into a scalar FP division by
scalarizeBinOpOfSplats it may be cheaper, but it looks like this is predicated
on the isExtractVecEltCheap TLI function which is implemented for x86 but not
AArch64. Perhaps for now combineRepeatedFPDivisors should only scale num uses
by splat if the division can be converted into scalar op.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D118343
2022-01-28 17:01:08 +00:00
Michał Górny ac666d1799 [lldb] [gdb-remote] Support getting siginfo via API
Add Thread::GetSiginfo() and SBThread::GetSiginfo() methods to retrieve
the siginfo value from server.

Differential Revision: https://reviews.llvm.org/D118055
2022-01-28 17:47:47 +01:00
Siva Chandra Reddy a858e25f1c [libc][NFC] Create file with all permissions for the user in read_write_test. 2022-01-28 16:41:52 +00:00
Jake Egan 6f4f745668 [clang][deps] Adapt test to be compatible when the assembler is called by default
When `-fno-integrated-as` is in effect (the default on AIX) the cc1 job produces a `.s` file instead. This patch adapts the test to accept `.s` or `.o` files.

Reviewed By: jansvoboda11

Differential Revision: https://reviews.llvm.org/D118152
2022-01-28 11:40:16 -05:00
Arjun P 6db019582a [MLIR] Introduce LexSimplex to support lexicographic optimization
This patch introduces a class LexSimplex that can currently be used to find the
lexicographically minimal rational point in an IntegerPolyhedron. This is a
series of patches leading to computing the lexicographically minimal integer
lattice point as well parametric lexicographic minimization.

Reviewed By: Groverkss

Differential Revision: https://reviews.llvm.org/D117437
2022-01-28 22:06:58 +05:30
David Tenty 9939bb6682 [NFC][AIX][clang] un-XFAIL gcc profile flag compat test
We can pass this test now thanks to recent changes that allow us to use PGO without LTO, so un-XFAIL the test and update the comments.

Differential Revision: https://reviews.llvm.org/D118474
2022-01-28 11:18:55 -05:00
Augusto Noronha b414954a5f [lldb] Make ReadCStringFromMemory default to read from the file-cache.
Differential Revision: https://reviews.llvm.org/D118265
2022-01-28 13:08:30 -03:00
Kito Cheng a9d5bb926d [RISCV] Use __extendhfsf2/__truncsfhf2 for fp16 <-> fp32
`__gnu_h2f_ieee` and `__gnu_f2h_ieee` are introduce by ARM and set that as
default name for fp16 and fp32 conversion in LLVM.

However RISC-V GCC using default naming scheme for that, which is
`__extendhfsf2` and `__truncsfhf2` for that, that cause runtime ABI
incompatible issue.

Although we didn't have formal runtime ABI spec to specify those naming
convention yet, but I think it would be great to fix the incompatible
issue first.

And I've plan to create a runtime ABI spec undere psABI spec this year.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D118207
2022-01-29 00:01:00 +08:00
Nikita Popov 7d176844d0 [CodeExtractor] Fix warning in assert (NFC) 2022-01-28 16:33:34 +01:00
Nikita Popov cf0357a545 [BasicBlockUtils] Fix typo in API name (NFC)
detatch -> detach. As this requires touching all uses, also
lower-case it in accordance with the style guide.
2022-01-28 16:32:13 +01:00
Nikita Popov 8a4293f3ef [Loads] Require Align in isDereferenceableAndAlignedPointer() (NFC)
Now that loads always have an alignment, we should not perform an
ABI alignment fallback here.
2022-01-28 16:23:32 +01:00
Sanjay Patel b4b97ec813 [x86] try harder to scalarize a vector load with extracted integer op uses
extract_vec_elt (load X), C --> scalar load (X+C)

As noted in the comment, DAGCombiner has this fold -- and the code in this
patch is adapted from DAGCombiner::scalarizeExtractedVectorLoad() -- but
x86 should benefit even if the loaded vector has other uses as long as we
apply some other x86-specific conditions. The motivating example from #50310
is shown in vec_int_to_fp.ll.

Fixes #50310

Differential Revision: https://reviews.llvm.org/D118376
2022-01-28 10:22:52 -05:00
Alex Bradbury 588f121ada [RISCV][NFC] Make Zb* instruction naming match the convention used elsewhere in the RISC-V backend
Where the instruction mnemonic contains a dot, we name the corresponding
instruction in the .td file using a _ in the place of the dot. e.g. LR_W
rather than LRW. This commit updates RISCVInstrInfoZb.td to follow that
convention.
2022-01-28 15:20:37 +00:00
eopXD 5f856c5b30 [NFC][RISCV] Bundle up ISAInfo updates and checks
Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D118334
2022-01-28 07:13:24 -08:00
Nikita Popov 0ebbf3435f [ArgPromotion] Don't assume all entry block instrs are executed
We should abort this walk if we hit any instruction that is not
guaranteed to transfer.
2022-01-28 16:08:42 +01:00
Nikita Popov 2dc45bf4de [ArgPromotion] Add test for non-willreturn load hoisting (NFC)
In this case, we have no guarantee that the load is unconditionally
executed, so the argument promotion is not legal.
2022-01-28 16:08:42 +01:00
Jeremy Morse 76fd78b4b3 [MVerifier] Don't check liveness of any debug instruction operands
Shiny new DBG_PHI instruction usually have physical registers as operands
-- however, the machine verifier checks to see whether they're live, and
occasionally this fails. There's a filter for DBG_VALUE instructions to not
get verified in this way: expand it to exempt all debug instructions from
liveness checking, which means DBG_PHIs get treated like DBG_VALUEs.

This also future proofs against us adding new debug instructions.

Differential Revision: https://reviews.llvm.org/D117891
2022-01-28 15:04:54 +00:00
Jay Foad de37912f00 [update_test_checks] Fix option name in warning message 2022-01-28 14:45:47 +00:00
Simon Pilgrim c7bb3665a1 [X86] SimplifyDemandedBitsForTargetNode - fold MOVMSK(YMM) -> MOVMSK(XMM)
If we don't demand the upper elements of the 256-bit vector, then just perform as a 128-bit vector
2022-01-28 14:42:53 +00:00
Simon Pilgrim 9d75ee1cd5 [Sema] Add signed/unsigned integer mismatch tests for min/max elementwise builtins
As suggested on D117898

Differential Revision: https://reviews.llvm.org/D118464
2022-01-28 14:31:36 +00:00
Nikita Popov 8b36c437df [ArgPromotion] Make areFunctionArgsABICompatible() static (NFC)
This function used to be shared with the Attributor, but can now
be made private.
2022-01-28 15:26:36 +01:00
Amy Kwan 9cc5b064f1 [PowerPC] Update handling of splat loads for v4i32/v4f32/v2i64 to require non-extending loads.
This patch updates how splat loads handled and is an extension of D106555.

Particularly, for v2i64/v4f32/v4i32 types, they are updated to handle only
non-extending loads. For v8i16/v16i8 types, they are updated to handle extending
loads only if the memory VT is the same vector element VT type.

A test case has been added to illustrate a scenario where a PPCISD::LD_SPLAT
node should not be produced. In this test, it depicts the following f64
extending load used in a v2f64 build vector, but the extending load is actually
used in more places other than the build vector (such as in t12 and t16).
```
Type-legalized selection DAG: %bb.0 'test:entry'
SelectionDAG has 20 nodes:
  t0: ch = EntryToken
  t4: i64,ch = CopyFromReg t0, Register:i64 %1
  t6: i64,ch = CopyFromReg t0, Register:i64 %2
  t11: f64,ch = load<(load (s64) from %ir.b, !tbaa !7)> t0, t4, undef:i64
        t16: f64 = fadd t31, t37
      t34: ch = store<(store (s64) into %ir.c, !tbaa !7)> t31:1, t16, t6, undef:i64
    t36: ch = TokenFactor t34, t37:1
    t27: v2f64 = BUILD_VECTOR t37, t37
  t22: ch,glue = CopyToReg t36, Register:v2f64 $v2, t27
      t12: f64 = fadd t11, t37
    t28: ch = store<(store (s64) into %ir.b, !tbaa !7)> t11:1, t12, t4, undef:i64
  t31: f64,ch = load<(load (s64) from %ir.c, !tbaa !7)> t28, t6, undef:i64
    t2: i64,ch = CopyFromReg t0, Register:i64 %0
  t37: f64,ch = load<(load (s32) from %ir.a, !tbaa !3), anyext from f32> t0, t2, undef:i64
  t23: ch = PPCISD::RET_FLAG t22, Register:v2f64 $v2, t22:1
```

Differential Revision: https://reviews.llvm.org/D117803
2022-01-28 08:23:01 -06:00
David Truby 81bd67e18a
[AArch64][SVE][VLS] Move extends into arguments of comparisons
When a comparison is extended and it would be free to extend the
arguments to that comparison, we can propagate the extend into those arguments.
This prevents extra instructions being generated to extend the result of the
comparison, which is not free to extend.

This is a resubmission of D116812 with fixes that need another review.

Differential Revision: https://reviews.llvm.org/D118139
2022-01-28 14:16:08 +00:00
Matt Morehouse f7c28332de [HWASan] Leave pointer tagged when calling memmove.
Fixes a false positive that occurs when a user-implemented memmove is
instrumented by HWASan.

Reviewed By: vitalybuka

Differential Revision: https://reviews.llvm.org/D118180
2022-01-28 06:15:38 -08:00
Sanjay Patel e9768a2a44 [x86] add test for possible load scalarization fold; NFC
This is a minimal test to show a transform proposed in D118376.
2022-01-28 08:49:37 -05:00
Valentin Clement 6277b90992
[flang] Add missing FIRBuilder library
Fix buildbot failure https://lab.llvm.org/buildbot/#/builders/160
2022-01-28 14:46:24 +01:00
Aaron Ballman b6d9ca14c2 Do not crash when trying to encode a _BitInt type
Using a _BitInt (or _ExtInt) type as a block parameter or block return
type hits an "unreachable" when trying to determine the encoding for
the block. Instead of crashing, this patch handles it like some of the
other types for which we don't yet have an encoding. The test case
verifies we no longer crash, but does not verify that we provide any
particular encoding (it can be updated once someone more familiar with
ObjC steps in to define the encoding).

Fixes PR50503.
2022-01-28 08:38:01 -05:00
Simon Pilgrim 2a13beaa70 [X86] combineSetCCMOVMSK - don't fold MOVMSK(BITCAST(PCMPEQ(X,0))) -> PTESTZ(X,X) if we're not testing every element comparison 2022-01-28 13:22:37 +00:00
Simon Pilgrim 835a737887 [X86] Add test showing incorrect movmsk->ptest fold
We can't fold MOVMSK(BITCAST(PCMPEQ(X,0))) -> PTESTZ(X,X) if we're not testing every element comparison
2022-01-28 13:22:36 +00:00
Paul Walker 49178a2c4e [SVE] Extend isel pattern coverage for BIC.
Adds patterns of the form "(and a, (not b)) -> bic".

NOTE: With this support I'm inclined to remove AArch64ISD::BIC,
but will leave that investigation for another time.

Differential Revision: https://reviews.llvm.org/D118365
2022-01-28 13:14:46 +00:00
Sander de Smalen cc8e3dadc4 [AArch64][SVE] NFC: Add test for scaled stepvector.
This commutative test could be optimised into:
  index z0.d, x0, x1

But currently isn't yet.
2022-01-28 13:08:15 +00:00
Bjorn Pettersson bcdcf984cc [test][NewGVN] Use '-passes=newgvn' instead of '-basic-aa -newgvn'
This updates NewGVN test cases that were running
  "opt -basic-aa -newgvn ..."
to run
  "opt -passes=newgvn ..."
instead.

The pipeline will be more similar to what we used to have with
legacy PM by doing it this way. The compatility mode that we've
been using for awhile during transition from legacy PM to new PM,
i.e. using the legacy syntax together with new PM, has resulted in
a pipeline such as
  -passes='function(require<basic-aa>),function(newgvn)'
but running the analysis in a separate function pass manager seem
overly complicated for these tests.

Another difference is that we will get the default aa-pipeline instead
of only running basic-aa. That might be a bit questioned (given that
the tests originally specified basic-aa). The output is however
identival for all the test cases modified here regardless of using
basic-aa or the default aa-pipeline.

This is also another small step towards removal of the support for
using the legacy PM syntax in opt.

Differential Revision: https://reviews.llvm.org/D118340
2022-01-28 13:58:22 +01:00
Bjorn Pettersson 4f73528403 [test][NewGVN] Use -passes=newgvn instead of -newgvn
Use the new PM syntax when specifying the pipeline in regression
tests previously running
  "opt -newgvn ..."

Instead we now do
  "opt -passes=newgvn ..."

Notice that this also changes the aa-pipeline to become the default
aa-pipeline instead of just basic-aa. Since these tests haven't been
explicitly requesting basic-aa in the past (compared to the test cases
updated in a separate patch involving "-basic-aa -newgvn") it is
assumed that the exact aa-pipeline isn't important for the validity
of the test cases. An alternative could have been to add
-aa-pipeline=basic-aa as well to the run lines, but that might just
add clutter in case the test cases do not care about the aa-pipeline.

This is another step to move away from the legacy PM syntax when
specifying passes in opt.

Differential Revision: https://reviews.llvm.org/D118341
2022-01-28 13:58:22 +01:00
Fraser Cormack 10879c26a2 [RISCV] Add tests for possible splat optimizations
These splats -- whether BUILD_VECTOR or SPLAT_VECTOR -- are formed by
first extracting a value from a vector and splatting it to all elements
of the destination vector. These could be performed more optimally,
avoiding the drop to scalar, using RVV's vrgather, for example.
2022-01-28 12:32:29 +00:00
Fraser Cormack 6297f929f7 [RISCV] Fix FileCheck prefixes in RVV test
The LMULMAX check names didn't match the options we were passing to llc
(they were swapped around) and we were silently missing coverage for one
test which differs between RV32 and RV64.
2022-01-28 12:08:30 +00:00
Milica Matic 402f91bcbb [llvm-mca] Plot as result of comparing multiple files
This patch introduces a new options for script llvm-mca-compare.py
(-plot-resource-pressure, -plot) to draw plots for llvm-mca tool
statistics and option (--plot-path) to specify relative path where
you want to save the plots.

Differential Revision: https://reviews.llvm.org/D115718
2022-01-28 13:04:52 +01:00
Simon Pilgrim cce6490eca [X86] combineSetCCMOVMSK - match all_of patterns with X86ISD::CMP as well as X86ISD::SUB
Previous folds by combineSetCCMOVMSK might have converted these to CMP when changing the bitwidth, and the CMP->SUB fold might not have happened (or will happen)
2022-01-28 11:43:10 +00:00