Commit Graph

822 Commits

Author SHA1 Message Date
Jim Grosbach 6caa557ae6 Clean up predicates on ARM target instruction aliases.
llvm-svn: 138249
2011-08-22 18:04:24 +00:00
Jim Grosbach 854fe433d4 Fix predicate for imm1_32
llvm-svn: 137865
2011-08-17 21:01:11 +00:00
Owen Anderson 61a3ece665 Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
llvm-svn: 137641
2011-08-15 20:08:25 +00:00
Owen Anderson 2d1d7a11f8 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.
llvm-svn: 137502
2011-08-12 20:36:11 +00:00
Owen Anderson 60138eaf93 Fix decoding of ARM-mode STRH.
llvm-svn: 137499
2011-08-12 20:02:50 +00:00
Owen Anderson 1043e173bc Specify fixed bit in the LDRBT encoding, which allows us to distinguish it from certain USAT16 encodings.
llvm-svn: 137494
2011-08-12 19:41:29 +00:00
Owen Anderson 3987a61c16 Fix decoding of pre-indexed stores.
llvm-svn: 137487
2011-08-12 18:12:39 +00:00
Owen Anderson c5798a3a59 Separate decoding for STREXD and LDREXD to make each work better.
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
Jim Grosbach 37f7e6b2f4 Remove no-longer-true comments. These are for the assembler, also.
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
Jim Grosbach e25942154c ARM STRT assembly parsing and encoding.
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
Owen Anderson eca346ee1a Make the USAT16 operand decoder auto-generate-able.
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
Owen Anderson f05e744857 Making SEL decodings auto-generate-able.
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
Jim Grosbach 88981ff168 Tidy up comment.
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
Owen Anderson b685c9f011 Fix decoding support for STREXD and LDREXD.
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding.
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Jim Grosbach 2ea19d1438 Tidy up. Remove unused template parameter.
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding.
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson 6066340301 Continue to tighten decoding by performing more operand validation.
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach 1b0f79573e Tidy up.
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach 2a50260f2f ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding.
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson 0e15b48f3c Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Jim Grosbach d5d6359785 ARM LDRT assembly parsing and encoding.
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach d3f7bcd43c Tidy up. 80 columns.
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support.
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support.
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson 1531e5cd2b Tabs --> spaces.
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson 8059f0cf8d Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Owen Anderson 92b942b1b5 Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson e008931bf6 Tighten operand checking on memory barrier instructions.
llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson 3d2e0e9db6 Tighten operand checking on CPS instructions.
llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson 042619f97d Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Owen Anderson e0152a73c2 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Jim Grosbach cab35c0836 ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.

llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
2011-08-05 21:28:30 +00:00
Jim Grosbach f0c95cadc7 ARM refactor indexed store instructions.
Refactor STR[B] pre and post indexed instructions to use addressing modes for
memory operands, which is necessary for assembly parsing and is more consistent
with the rest of the memory instruction definitions. Make some incremental
progress on refactoring away the mega-operand addrmode2 along the way, which
is nice.

llvm-svn: 136978
2011-08-05 20:35:44 +00:00
Jim Grosbach bafce840ff ARM use a dedicated printer for postidx_reg operands.
llvm-svn: 136968
2011-08-05 15:48:21 +00:00
Jim Grosbach cd17c12078 ARM assembly parsing and encoding for LDR instructions.
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940
2011-08-04 23:01:30 +00:00
Owen Anderson ce5190321e LDCL_POST and STCL_POST need one's-complement offsets, rather than two's complement offsets. Add an appropriate immediate type for them.
llvm-svn: 136896
2011-08-04 18:24:14 +00:00
Jim Grosbach d359571120 ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Jim Grosbach c8c63914c5 Tidy up. 80 columns.
llvm-svn: 136705
2011-08-02 18:16:36 +00:00
Jim Grosbach 9ec152b6bf ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting.

llvm-svn: 136704
2011-08-02 18:07:32 +00:00
Jim Grosbach 9f620a6883 Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.
llvm-svn: 136656
2011-08-01 22:02:20 +00:00
Jim Grosbach 0f731b3232 Fix comments.
llvm-svn: 136655
2011-08-01 21:55:12 +00:00
Jim Grosbach 51726e2147 ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.

llvm-svn: 136509
2011-07-29 20:26:09 +00:00
Jim Grosbach e537438ca5 ARM CPS mode immediate is 5 bits, not 4.
llvm-svn: 136505
2011-07-29 20:02:39 +00:00
Jim Grosbach c4dc52cd52 ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.

llvm-svn: 136479
2011-07-29 18:47:24 +00:00
Jim Grosbach 20d38124a2 ARM SRS and RFE instructions are not code-gen only.
llvm-svn: 136475
2011-07-29 17:51:39 +00:00
Jim Grosbach 3b764cfd48 ARM range checking for mode on CPS instruction.
llvm-svn: 136473
2011-07-29 17:42:17 +00:00