Commit Graph

70386 Commits

Author SHA1 Message Date
Daniel Sanders e898236bc2 [mips][mips64r6] daddi is not available on MIPS64r6
Summary:
It's not emitted by the code generator so we only need assembler tests.

Also added missing daddi aliases from dsub mnemonics, and removed a couple
duplicate dsub tests.

Depends on D4112

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4113

llvm-svn: 210897
2014-06-13 12:49:06 +00:00
Cameron McInally c43c8f9458 Add HasCDI predicate to AVX512 VPBROADCASTM*.
llvm-svn: 210892
2014-06-13 11:40:31 +00:00
Tim Northover 24fe2322a2 CPP backend: set volatile property on atomic instructions.
llvm-svn: 210890
2014-06-13 09:14:50 +00:00
Oliver Stannard b5e596f7c3 ARM: Fix fastcc calling convention for Thumb1
When targetting Thumb1 on a processor which has a VFP unit (which
is not accessible from Thumb1), we were converting the fastcc calling
convention to AAPCS-VFP, which is not possible.

llvm-svn: 210889
2014-06-13 08:33:03 +00:00
Matt Arsenault c02eea7f64 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

llvm-svn: 210888
2014-06-13 07:44:38 +00:00
Matt Arsenault 825fb0b094 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
2014-06-13 04:00:30 +00:00
Rafael Espindola b4ad29be92 Fix build on windows.
llvm-svn: 210873
2014-06-13 02:36:09 +00:00
Rafael Espindola db4ed0bdab Remove 'using std::errro_code' from lib.
llvm-svn: 210871
2014-06-13 02:24:39 +00:00
Juergen Ributzka 3453bcf64d [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.
This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding
insertelement instructions are folded into the conversion instruction (if
possible).

llvm-svn: 210870
2014-06-13 02:21:58 +00:00
Tom Stellard 2e59a45f80 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
llvm-svn: 210869
2014-06-13 01:32:00 +00:00
Tom Stellard d881e9195a R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
llvm-svn: 210868
2014-06-13 01:31:56 +00:00
Rafael Espindola bff5d0d16a Remove all uses of 'using std::error_code' from headers.
llvm-svn: 210866
2014-06-13 01:25:41 +00:00
Tom Stellard bfd480d79f R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
llvm-svn: 210865
2014-06-13 01:02:57 +00:00
Juergen Ributzka 454d374e37 [FastISel][X86] - Add branch weights
Add branch weights to branch instructions, so that the following passes can
optimize based on it (i.e. basic block ordering).

llvm-svn: 210863
2014-06-13 00:45:11 +00:00
Eric Christopher 030294e4c5 Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.
llvm-svn: 210862
2014-06-13 00:20:39 +00:00
Eric Christopher a47f6804d2 Move to a private function to initialize subtarget dependencies
so we can use initializer lists for the ARMSubtarget and then
use this to initialize a moved DataLayout on the subtarget from
the TargetMachine.

llvm-svn: 210861
2014-06-13 00:20:35 +00:00
Alexey Samsonov 0670cfaf01 [DWARF parser] Fix broken address ranges construction.
Previous algorithm for constructing [Address ranges]->[Compile Units]
mapping was wrong. It somewhat relied on the assumption that address ranges
for different compile units may not overlap. It is not so.
For example, two compile units may contain the definition of the same
linkonce_odr function. These definitions will be merged at link-time,
resulting in equivalent .debug_ranges entries for both these units

Instead of sorting and merging original address ranges (from .debug_ranges
and .debug_aranges), implement a different approach: save endpoints
of all ranges, and then use a sweep-line approach to construct
the desired mapping. If we find that certain address maps to
several compilation units, we just pick any of them.

llvm-svn: 210860
2014-06-12 23:58:49 +00:00
Eric Christopher 70e005a171 Have ARMSelectionDAGInfo take a DataLayout as it's argument as the
DAG has access to the subtarget and TargetSelectionDAGInfo only
needs a DataLayout.

llvm-svn: 210859
2014-06-12 23:39:49 +00:00
Juergen Ributzka 349777d3ea [FastISel][X86] Add MachineMemOperand to load/store instructions.
This commit adds MachineMemOperands to load and store instructions. This allows
the peephole optimizer to fold load instructions. Unfortunatelly the peephole
optimizer currently doesn't run at -O0.

llvm-svn: 210858
2014-06-12 23:27:57 +00:00
Eric Christopher 02ae6902fa Move the PPCSelectionDAGInfo off the TargetMachine and onto the
subtarget.

llvm-svn: 210854
2014-06-12 23:02:32 +00:00
Eric Christopher e47dcd411a Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachine
since that's all it needs.

llvm-svn: 210853
2014-06-12 22:56:48 +00:00
Eric Christopher f8c031fccf Move PPCTargetLowering off of the TargetMachine and onto the subtarget.
llvm-svn: 210852
2014-06-12 22:50:10 +00:00
Eric Christopher d90a8746df Remove an extraneous this-> to access the subtarget.
llvm-svn: 210849
2014-06-12 22:38:20 +00:00
Eric Christopher b1aaebecb1 Rename PPCSubTarget to Subtarget in PPCTargetLowering for consistency.
Also remove an extra local subtarget in the initialization functions.

llvm-svn: 210848
2014-06-12 22:38:18 +00:00
Andrew Trick 491e34a139 Fix the scheduler's MaxObservedStall computation.
WenHan Gu pointed out this bug that results in an assert
not being effective in some cases.

llvm-svn: 210846
2014-06-12 22:36:28 +00:00
Eric Christopher f55a224920 Move PPCJITInfo off of the TargetMachine and onto the subtarget.
Needed to migrate a few functions around to avoid circular header
dependencies.

llvm-svn: 210845
2014-06-12 22:28:06 +00:00
Eric Christopher 54367e01cc Remove the use of TargetMachine from PPCJITInfo and replace with
the subtarget. Also remove unnecessary argument to the constructor
at the same time, we already have access via the subtarget.

llvm-svn: 210844
2014-06-12 22:19:51 +00:00
Eric Christopher bd14dc519c Move PPCInstrInfo off of the target machine and onto the subtarget.
llvm-svn: 210839
2014-06-12 22:05:46 +00:00
Rafael Espindola adccf860ac Try to fix the windows build.
llvm-svn: 210837
2014-06-12 21:53:57 +00:00
Eric Christopher 1dcea73540 Remove TargetMachine from PPCInstrInfo and all dependencies and
replace with the current subtarget.

llvm-svn: 210836
2014-06-12 21:48:52 +00:00
Rafael Espindola 3acea39853 Don't use 'using std::error_code' in include/llvm.
This should make sure that most new uses use the std prefix.

llvm-svn: 210835
2014-06-12 21:46:39 +00:00
Duncan P. N. Exon Smith fd5c553f54 GVN: Enable value forwarding for calloc
Enable value forwarding for loads from `calloc()` without an intervening
store.

This change extends GVN to handle the following case:

    %1 = tail call noalias i8* @calloc(i64 1, i64 4)
    %2 = bitcast i8* %1 to i32*
    ; This load is trivially constant zero
    %3 = load i32* %2, align 4

This is analogous to the handling for `malloc()` in the same places.
`malloc()` returns `undef`; `calloc()` returns a zero value.  Note that
it is correct to return zero even for out of bounds GEPs since the
result of such a GEP would be undefined.

Patch by Philip Reames!

llvm-svn: 210828
2014-06-12 21:16:19 +00:00
Matt Arsenault 5d47d4ac7e R600: Mostly remove remaining AMDIL intrinsics.
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
2014-06-12 21:15:44 +00:00
Eric Christopher 49628bc4ff Move DataLayout from the PPCTargetMachine to the subtarget.
llvm-svn: 210824
2014-06-12 21:08:06 +00:00
Eric Christopher d104c31fc0 Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. Use
the initializeSubtargetDependencies code to obtain an initialized
subtarget and migrate a couple of subtarget using functions to the
.cpp file to avoid circular includes.

llvm-svn: 210822
2014-06-12 20:54:11 +00:00
Juergen Ributzka a13cab5b74 [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.
Recommit with fixed argument attribute checking code, which is required to bail
out of all the cases we don't handle yet.

llvm-svn: 210815
2014-06-12 20:12:34 +00:00
Saleem Abdulrasool 65ca57a418 CodeGen: enable mov.w/mov.t pairs with minsize for WoA
Windows on ARM uses COFF/PE which is intrinsically position independent.  For
the case of 32-bit immediates, use a pair-wise relocation as otherwise we may
exceed the range of operators.  This fixes a code generation crash when using
-Oz when targeting Windows on ARM.

llvm-svn: 210814
2014-06-12 20:06:33 +00:00
Juergen Ributzka 5ad463f55e Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point arguments."
Reverting it because it breaks several tests.

llvm-svn: 210810
2014-06-12 19:21:43 +00:00
Alexey Samsonov f0e4034c42 [llvm-symbolizer] Fix parsing DW_AT_ranges in Fission skeleton compile unit DIEs.
Turns out that DW_AT_ranges_base attribute sets the offset for
DW_AT_ranges values specified in the .dwo file, but not for DW_AT_ranges specified
in the skeleton compile unit DIE in the main executable. This is extremely confusing,
and would hopefully be fixed in DWARF-5 when it's finalized. For now this
behavior makes sense, as otherwise Fission would break DWARF consumers who
doesn't know anything about DW_AT_ranges_base.

llvm-svn: 210809
2014-06-12 18:52:35 +00:00
Eli Bendersky dc6de2ce29 Revert r210721 as it causes breakage in internal builds (and possibly GDB).
llvm-svn: 210807
2014-06-12 18:05:39 +00:00
Saleem Abdulrasool 3c890c4ad6 X86: stifle GCC warning
lib/Target/X86/X86TargetTransformInfo.cpp: In member function ‘virtual unsigned int {anonymous}::X86TTI::getIntImmCost(unsigned int, unsigned int, const llvm::APInt&, llvm::Type*) const’:
lib/Target/X86/X86TargetTransformInfo.cpp:920:60: warning: enumeral and non-enumeral type in conditional expression [enabled by default]

This seems like an unhelpful warning, but there doesnt seem to be a controlling
flag, so add an explicit cast to silence the warning.

llvm-svn: 210806
2014-06-12 17:56:18 +00:00
Rafael Espindola 885719f027 Trying to fix the windows build.
llvm-svn: 210805
2014-06-12 17:49:35 +00:00
Rafael Espindola a6e9c3e43a Remove system_error.h.
This is a minimal change to remove the header. I will remove the occurrences
of "using std::error_code" in a followup patch.

llvm-svn: 210803
2014-06-12 17:38:55 +00:00
Artyom Skrobov 8bafe4b942 adding re-include guards into lib/Support/reg*.h
llvm-svn: 210794
2014-06-12 16:07:56 +00:00
Zachary Turner 0921f6bdb8 Remove pimpl class from PassRegistry.
Since removeRegistrationListener is no longer called during static
destruction, we can get rid of the pimpl in PassRegistry.

This should clean up the code somewhat, increase clarity, and also
allows us to put the Lock as a member of the class, instead of as a
ManagedStatic.

As part of this change, the PassInfo class is moved from
PassSupport.h to its own file, to eliminate the otherwise circular
header dependency between PassRegistry.h and PassSupport.h

Reviewed by: rnk, dblaikie

Differential Revision: http://reviews.llvm.org/D4107

llvm-svn: 210793
2014-06-12 16:06:51 +00:00
Tom Stellard 7783b0adf4 Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors"
This reverts commit r210540, adds a testcase for the regression it
caused, and marks the R600 test it was supposed to fix as XFAIL.

llvm-svn: 210792
2014-06-12 16:04:47 +00:00
James Molloy 1417b0be3e Disable the load/store optimization pass for Thumb-1.
Moritz's changes have improved codegen a lot, but further testing showed significant correctness problems. Disable by default until these have been worked out.

Patch by Moritz Roth!

llvm-svn: 210789
2014-06-12 15:18:33 +00:00
Daniel Sanders 3d3ea53f32 [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6
Summary:
Also tightened up the acceptable condition operand for these instructions
on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior
to that only $fcc0 is acceptable.

We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's
probably best to do this in InstCombine.

Depends on D4111

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4112

llvm-svn: 210787
2014-06-12 15:00:17 +00:00
Daniel Sanders 39a1ca75ba [mips][mips64r6] bc2[ft] are not available on MIPS32r6/MIPS64r6
Summary:
These instructions are not implemented for any MIPS ISA so we only need
testcases.

Depends on D4110

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4111

llvm-svn: 210786
2014-06-12 14:54:13 +00:00
Daniel Sanders fd61fd3b6f [mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6
Summary:
Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in
mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed
by getelementptr). This does not affect the purpose of the test.

Depends on D4004

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4110

llvm-svn: 210784
2014-06-12 14:19:28 +00:00
Rafael Espindola 0a5f9cf50d Replace llvm::error_code with std::error_code.
llvm-svn: 210783
2014-06-12 14:11:22 +00:00
Dinesh Dwivedi 95f0d51bd3 This removes TODO added in http://reviews.llvm.org/D3658
The patch transforms

ABS(NABS(X)) -> ABS(X)
NABS(ABS(X)) -> NABS(X)

Differential Revision: http://reviews.llvm.org/D4040

llvm-svn: 210782
2014-06-12 14:06:00 +00:00
Daniel Sanders 6c97d979df [mips][mips64r6] prefx is not available on MIPS32r6/MIPS64r6
Summary: We haven't implemented this instruction so we only add a test case.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D4004

llvm-svn: 210779
2014-06-12 13:51:27 +00:00
Daniel Sanders 557889affd [mips][mips64r6] 80 col corrections that should have been in r210777.
llvm-svn: 210778
2014-06-12 13:42:04 +00:00
Daniel Sanders 0fa6041625 [mips][mips64r6] c.cond.fmt, mov[fntz], and mov[fntz].[ds] are not available on MIPS32r6/MIPS64r6
Summary:
c.cond.fmt has been replaced by cmp.cond.fmt. Where c.cond.fmt wrote to
dedicated condition registers, cmp.cond.fmt writes 1 or 0 to normal FGR's
(like the GPR comparisons).

mov[fntz] have been replaced by seleqz and selnez. These instructions
conditionally zero a register based on a bool in a GPR. The results can
then be or'd together to act as a select without, for example, requiring a third
register read port.

mov[fntz].[ds] have been replaced with sel.[ds]

MIPS64r6 currently generates unnecessary sign-extensions for most selects.
This is because the result of a SETCC is currently an i32. Bits 32-63 are
undefined in i32 and the behaviour of seleqz/selnez would otherwise depend
on undefined bits. Later, we will fix this by making the result of SETCC an
i64 on MIPS64 targets.

Depends on D3958

Reviewers: jkolek, vmedic, zoran.jovanovic

Reviewed By: vmedic, zoran.jovanovic

Differential Revision: http://reviews.llvm.org/D4003

llvm-svn: 210777
2014-06-12 13:39:06 +00:00
Daniel Sanders 559dd851b6 [mips][mips64r6] jalx is not available on MIPS32r6/MIPS64r6
Summary: Depends on D3957

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3958

llvm-svn: 210775
2014-06-12 12:58:20 +00:00
Zoran Jovanovic b9c07f3b86 [mips][mips64r6] Add R_MIPS_PC19_S2
Differential Revision: http://reviews.llvm.org/D3866

llvm-svn: 210773
2014-06-12 12:40:00 +00:00
Rafael Espindola ed6882b835 Don't import make_error_code into the llvm namespace.
llvm-svn: 210772
2014-06-12 11:58:49 +00:00
Daniel Sanders 1f6f0f4b54 [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and FP64
Summary:
To make this work for both AFGR64 and FGR64 register sets, I've had to make the
instruction definition consistent with the white lie (that it reads the lower
32-bits of the register) when they are generated by expandBuildPairF64().

Corrected the definition of hasMips32r2() and hasMips64r2() to include
MIPS32r6 and MIPS64r6.

Depends on D3956

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3957

llvm-svn: 210771
2014-06-12 11:55:58 +00:00
Zoran Jovanovic 28a0ca0759 [mips][mips64r6] Add bgec and bgeuc instructions
Differential Revision: http://reviews.llvm.org/D4017

llvm-svn: 210770
2014-06-12 11:47:44 +00:00
Andrea Di Biagio 2dd3b3b674 [X86] Teach how to dump the name of target node RDTSCP_DAG.
When I originally added node RDTSCP_DAG (r207127) I forgot to add
a string name for it in method 'getTargetNodeName'.

No functional change intended.

llvm-svn: 210769
2014-06-12 11:37:24 +00:00
Daniel Sanders ded02af45e [mips][mips64r6] madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not available on MIPS32r6/MIPS64r6
Summary:
This patch updates both the assembler and the code generator.

MIPS32r6/MIPS64r6 replaces them with maddf.[ds] and msubf.[ds] which are fused
multiply-add/sub operations. We don't emit these yet, this patch only prevents the removed instructions from being emitted.

Depends on D3955

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3956

llvm-svn: 210763
2014-06-12 11:04:18 +00:00
Daniel Sanders 826f8b3d0c [mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6
Summary:
This patch disables madd/maddu/msub/msubu in both the assembler and code
generator.

Depends on D3896

Reviewers: jkolek, zoran.jovanovic, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3955

llvm-svn: 210762
2014-06-12 10:54:16 +00:00
Andrea Di Biagio 972ff97f8c [X86] Teach how to combine AVX and AVX2 horizontal binop on packed 256-bit vectors.
This patch adds target combine rules to match:
 - [AVX] Horizontal add/sub of packed single/double precision floating point
   values from 256-bit vectors;
 - [AVX2] Horizontal add/sub of packed integer values from 256-bit vectors.

llvm-svn: 210761
2014-06-12 10:53:48 +00:00
Daniel Sanders 308181eaa0 [mips][mips64r6] Replace m[tf]hi, m[tf]lo, mult, multu, dmult, dmultu, div, ddiv, divu, ddivu for MIPS32r6/MIPS64.
Summary:
The accumulator-based (HI/LO) multiplies and divides from earlier ISA's have
been removed and replaced with GPR-based equivalents. For example:
  div $1, $2
  mflo $3
is now:
  div $3, $1, $2

This patch disables the accumulator-based multiplies and divides for
MIPS32r6/MIPS64r6 and uses the GPR-based equivalents instead.

Renamed expandPseudoDiv to insertDivByZeroTrap to better describe the
behaviour of the function.

MipsDelaySlotFiller now invalidates the liveness information when moving
instructions to the delay slot. Without this, divrem.ll will abort since
%GP ends up used before it is defined.

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3896

llvm-svn: 210760
2014-06-12 10:44:10 +00:00
Matt Arsenault 2c81994f92 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
2014-06-12 08:21:54 +00:00
Juergen Ributzka 04558dc77a [FastISel] Add support for the stackmap intrinsic.
This implements target-independent FastISel lowering for the stackmap intrinsic.

llvm-svn: 210742
2014-06-12 03:29:26 +00:00
Rafael Espindola e5ec53ba96 Prefix generic_category with std::.
Sorry I missed these before.

llvm-svn: 210740
2014-06-12 02:52:22 +00:00
Rafael Espindola 7e577f73ee Don't put generic_category in the llvm namespace.
llvm-svn: 210737
2014-06-12 02:00:39 +00:00
Bob Wilson 2f7cc01895 Fix verifier for GlobalAliases to avoid recursing into global initializers.
The verifier follows GlobalAlias operands so that it can detect cycles of
alias definitions. It was doing this in a way that caused it to also recurse
through initializers for the GlobalValue aliasees, and it would fail when
an initializer refers to a global that is a declaration and not a definition.
This patch causes it to stop recursing when it hits a global definition.
<rdar://problem/17277451>

llvm-svn: 210734
2014-06-12 01:46:54 +00:00
Rafael Espindola 25188c95de Don't import error_category into the llvm namespace.
llvm-svn: 210733
2014-06-12 01:45:43 +00:00
Rafael Espindola acc5d7c911 Don't import error_condition into the llvm namespace.
llvm-svn: 210731
2014-06-12 01:29:42 +00:00
Rafael Espindola 116f21c4dd Used mapWindowsError. I missed these in the initial transition.
llvm-svn: 210729
2014-06-12 01:25:33 +00:00
Rafael Espindola adb73e6fb9 Try to fix the mingw build.
* MingW needs mapWindowsError.
* MingW is missing some entries in std::errc, but we don't use them.

llvm-svn: 210725
2014-06-12 00:24:39 +00:00
Zachary Turner 39c422da57 Do not register and de-register PassRegistrationListeners during
construction and destruction.

PassRegistrationListener is intended for use as a generic listener.
In some cases, PassRegistrationListener-derived classes were being
created, and automatically registered and de-registered in static
constructors and destructors.  Since ManagedStatics are destroyed
prior to program shutdown, this leads to errors where an attempt is
made to access a ManagedStatic that has already been destroyed.

Reviewed by: rnk, dblaikie

Differential Revision: http://reviews.llvm.org/D4106

llvm-svn: 210724
2014-06-12 00:16:36 +00:00
Eli Bendersky 899bef099f Teach LoopUnrollPass to respect loop unrolling hints in metadata.
See http://reviews.llvm.org/D4090 for more details.

The Clang change that produces this metadata was committed in r210667

Patch by Mark Heffernan.

llvm-svn: 210721
2014-06-11 23:15:35 +00:00
Juergen Ributzka 272b570a80 [FastISel][X86] Add support for the sqrt intrinsic.
llvm-svn: 210720
2014-06-11 23:11:02 +00:00
Juergen Ributzka fbaa3db909 [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.
llvm-svn: 210719
2014-06-11 23:10:58 +00:00
Zachary Turner a997d928fc Don't acquire the mutex during the destructor of PassRegistry.
This destructor is run as part of static program termination, and
so all ManagedStatics (including this lock) will have been
destroyed by llvm_shutdown.  Furthermore, if there is actually
a race condition during static program termination, then we are
just hiding a bug somewhere else, because other threads should
not be running at this point.

llvm-svn: 210717
2014-06-11 23:03:31 +00:00
Rafael Espindola da70bfd826 Implement get_magic with generic tools and inline it.
llvm-svn: 210716
2014-06-11 22:53:00 +00:00
Rafael Espindola 70fbe6f80e Remove unused has_magic.
This will allow inlining get_magic, which should in turn fix one of the mingw
build problems after the switch to std::error_code.

llvm-svn: 210712
2014-06-11 21:53:22 +00:00
Juergen Ributzka 4dc958777c [FastISel][X86] Add support for the frameaddress intrinsic.
llvm-svn: 210709
2014-06-11 21:44:44 +00:00
Chad Rosier 2205d4ef05 [AArch64] Basic Sched Model for Cortex-A57.
Patch by Dave Estes<cestes@codeaurora.org>
Differential Revision: http://reviews.llvm.org/D4008

llvm-svn: 210705
2014-06-11 21:06:56 +00:00
Tom Stellard 4a9cea608c R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
2014-06-11 20:51:42 +00:00
Tom Stellard 3fe21f8afa R600: BCNT_INT is a vector only instruction
llvm-svn: 210702
2014-06-11 20:51:39 +00:00
Jim Grosbach 7a930bf9ef ARM: honor hex immediate formatting for ldr/str i12 offsets.
Previously we would always print the offset as decimal, regardless of
the formatting requested. Now we use the formatImm() helper so the value
is printed as the client (LLDB in the motivating example) requested.

Before:
ldr.w r8, [sp, #180] @ always

After:
ldr.w r8, [sp, #0xb4] @ when printing hex immediates
ldr.w r8, [sp, #0180] @ when printing decimal immediates

rdar://17237103

llvm-svn: 210701
2014-06-11 20:26:45 +00:00
Matt Arsenault 2acc7a4570 R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
2014-06-11 19:31:13 +00:00
Rafael Espindola 5c4f829424 Use std::error_code instead of llvm::error_code.
The idea of this patch is to turn llvm/Support/system_error.h into a
transitional header that just brings in the erorr_code api to the llvm
namespace. I will remove it shortly afterwards.

The cases where the general idea needed some tweaking:

* std::errc is a namespace in msvc, so we cannot use "using std::errc". I could
add an #ifdef, but there were not that many uses, so I just added std:: to
them in this patch.

* Template specialization had to be moved to the std namespace in this
patch set already.

* The msvc implementation of default_error_condition doesn't seem to
provide the same transformations as we need. Not too surprising since
the standard doesn't actually say what "equivalent" means. I fixed the
problem by keeping our old mapping and using it at error_code
construction time.

Despite these shortcomings I think this is still a good thing. Some reasons:

* The different implementations of system_error might improve over time.
* It removes 925 lines of code from llvm already.
* It removes 6313 bytes from the text segment of the clang binary when
it is built with gcc and 2816 bytes when building with clang and
libstdc++.

llvm-svn: 210687
2014-06-11 19:05:50 +00:00
Chad Rosier 829cc2e7d9 Fix assert comments in Instruction.cpp.
llvm-svn: 210684
2014-06-11 18:26:29 +00:00
Matt Arsenault 845438204f R600/SI: Update place using old subtarget predicate
llvm-svn: 210683
2014-06-11 18:11:34 +00:00
Matt Arsenault caa0ec2851 R600/SI: Add common 64-bit LDS atomics
llvm-svn: 210680
2014-06-11 18:08:54 +00:00
Matt Arsenault 1f10c5e2c9 R600/SI: Add instruction definitions for 64-bit LDS atomics
llvm-svn: 210679
2014-06-11 18:08:50 +00:00
Matt Arsenault c793e1d9dc R600/SI: Add 32-bit LDS atomic cmpxchg
llvm-svn: 210678
2014-06-11 18:08:48 +00:00
Matt Arsenault 9e874541ac R600/SI: Use LDS atomic inc / dec
llvm-svn: 210677
2014-06-11 18:08:45 +00:00
Matt Arsenault 0e69e8128c R600/SI: Add other LDS atomic operations
llvm-svn: 210676
2014-06-11 18:08:42 +00:00
Matt Arsenault 8c6613d2bf R600/SI: Add instruction definitions for more LDS ops
llvm-svn: 210675
2014-06-11 18:08:39 +00:00
Matt Arsenault 7ddcd83d49 R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
2014-06-11 18:08:37 +00:00
Matt Arsenault 725741004c R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
2014-06-11 18:08:34 +00:00
Matt Arsenault 364a6747aa R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
2014-06-11 17:50:44 +00:00
Matt Arsenault 064c206d23 R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
2014-06-11 17:40:32 +00:00
Tim Northover 4dc9eaa6ba X86: add stringy name for X86ISD::LCMPXCHG16_DAG
I don't know what "target specific node #383" is, and I don't want to
have to.

llvm-svn: 210663
2014-06-11 17:04:08 +00:00
Eric Christopher 4fdc765b13 Revert r210613 to conform to coding standards.
Thanks Duncan for noticing.

llvm-svn: 210662
2014-06-11 16:59:33 +00:00
Matheus Almeida 595fcab2d0 [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4019

llvm-svn: 210654
2014-06-11 15:05:56 +00:00
Cameron McInally 5d1b7b94e4 Add AVX512 masked leadz instrinsic support.
llvm-svn: 210652
2014-06-11 12:54:45 +00:00
Andrea Di Biagio c7af75f9a7 [X86] Refactor the logic to select horizontal adds/subs to a helper function.
This patch moves part of the logic implemented by the target specific
combine rules added at r210477 to a separate helper function.
This should make easier to add more rules for matching AVX/AVX2 horizontal
adds/subs.

This patch also fixes a problem caused by a wrong check performed on indices
of extract_vector_elt dag nodes in input to the scalar adds/subs.

New tests have been added to verify that we correctly check indices of
extract_vector_elt dag nodes when selecting a horizontal operation.

llvm-svn: 210644
2014-06-11 07:57:50 +00:00
Jiangning Liu d623c528c5 Create macro INITIALIZE_TM_PASS.
Pass initialization requires to initialize TargetMachine for back-end
specific passes. This commit creates a new macro INITIALIZE_TM_PASS to
simplify this kind of initialization.

llvm-svn: 210641
2014-06-11 07:04:37 +00:00
Jiangning Liu b2ae37fb67 Global merge for global symbols.
This commit is to improve global merge pass and support global symbol merge.
The global symbol merge is not enabled by default. For aarch64, we need some
more back-end fix to make it really benifit ADRP CSE.

llvm-svn: 210640
2014-06-11 06:44:53 +00:00
Jiangning Liu 3e5b855a51 Rename global-merge to enable-global-merge.
llvm-svn: 210639
2014-06-11 06:35:26 +00:00
Craig Topper 213d2f79e5 Convert StringMapEntry::Create to use StringRef instead of start/end pointers. Simpliies all in tree call sites. No functional change.
llvm-svn: 210638
2014-06-11 05:35:56 +00:00
Rafael Espindola ace0080a4a Try to fix the msvc build.
llvm-svn: 210636
2014-06-11 04:41:37 +00:00
Rafael Espindola 181adb5f57 Uses generic_category instead of system_category.
Some c++ libraries (libstdc++ at least) don't seem to map to the generic
category in in the system_category's default_error_condition.

llvm-svn: 210635
2014-06-11 04:34:41 +00:00
Saleem Abdulrasool faa29bd529 MC: add enumeration of WinEH data encoding
Most Windows platforms use auxiliary data for unwinding.  This information is
stored in the .pdata section.  The encoding format for the data differs between
architectures and Windows variants.  Windows MIPS and Alpha use identical
formats; Alpha64 is the same with different widths.  Windows x86_64 and Itanium
share the representation.  All Windows CE entries are identical irrespective of
the architecture.  ARMv7 (Windows [NT] on ARM) has its own format.

This enumeration will become the differentiator once the windows EH emission
infrastructure is generalised, allowing us to emit the necessary unwinding
information for Windows on ARM.

llvm-svn: 210634
2014-06-11 04:19:25 +00:00
Rafael Espindola a813d608a9 Remove windows_error.
MSVC doesn't seem to provide any is_error_code_enum enumeration for the
windows errors.

Fortunately very few places in llvm have to handle raw windows errors, so
we can just construct the corresponding error_code directly.

llvm-svn: 210631
2014-06-11 03:58:34 +00:00
Rafael Espindola 6a9aae77d4 There is no posix_category in std, use generic_category.
llvm-svn: 210630
2014-06-11 03:49:13 +00:00
Matt Arsenault 10da3b2516 Use cast instead of assert + dyn_cast
llvm-svn: 210628
2014-06-11 03:30:06 +00:00
Matt Arsenault c9df794042 R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
2014-06-11 03:29:54 +00:00
Saleem Abdulrasool 8076cab0ce CodeGen: refactor DwarfException
DwarfException served as a base class for exception handling directive emission.
However, this is also used by other exception models (e.g. Win64EH).  Rename
this class to EHStreamer and split it out of DwarfException.h.  NFC.

Use the opportunity to fix up some of the documentation comments to match
current LLVM style.  Also rename some functions to conform better with current
LLVM coding style.

llvm-svn: 210622
2014-06-11 01:19:03 +00:00
Eric Christopher a475d5c54a Remove duplicate copy of InstrItineraryData from the TargetMachine,
it's already on the subtarget.

llvm-svn: 210619
2014-06-11 00:53:17 +00:00
Eric Christopher 7c9d4e058a Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the AArch64 Subtarget.

llvm-svn: 210616
2014-06-11 00:46:34 +00:00
Eric Christopher 1a2120312b Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the X86Subtarget.

llvm-svn: 210614
2014-06-11 00:25:19 +00:00
Eric Christopher 946a6581ea Sort includes.
llvm-svn: 210613
2014-06-11 00:25:16 +00:00
Juergen Ributzka 2dace6e54b [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.
llvm-svn: 210610
2014-06-10 23:52:44 +00:00
Eric Christopher cd996edec5 Use unique_ptr for X86Subtarget pointer members.
llvm-svn: 210606
2014-06-10 23:26:47 +00:00
Eric Christopher 841da85198 Move AArch64TargetLowering to AArch64Subtarget.
This currently necessitates a TargetMachine for the TargetLowering
constructor and TLOF.

llvm-svn: 210605
2014-06-10 23:26:45 +00:00
Zachary Turner 6610b99cb5 Revert "Remove support for runtime multi-threading."
This reverts revision r210600.

llvm-svn: 210603
2014-06-10 23:15:43 +00:00
Zachary Turner f6054ca18c Remove support for runtime multi-threading.
This patch removes the functions llvm_start_multithreaded() and
llvm_stop_multithreaded(), and changes llvm_is_multithreaded()
to return a constant value based on the value of the compile-time
definition LLVM_ENABLE_THREADS.

Previously, it was possible to have compile-time support for
threads on, and runtime support for threads off, in which case
certain mutexes were not allocated or ever acquired.  Now, if the
build is created with threads enabled, mutexes are always acquired.

A test before/after patch of compiling a very large TU showed no
noticeable performance impact of this change.

Reviewers: rnk

Differential Revision: http://reviews.llvm.org/D4076

llvm-svn: 210600
2014-06-10 23:01:20 +00:00
Eric Christopher f63bc64df5 Move AArch64InstrInfo to AArch64Subtarget.
llvm-svn: 210599
2014-06-10 22:57:25 +00:00
Eric Christopher 58f3266722 Remove a method that was just replacing direct access to a member.
llvm-svn: 210598
2014-06-10 22:57:21 +00:00
Eric Christopher 6c786a1dd1 Remove the use of TargetMachine from X86InstrInfo.
llvm-svn: 210596
2014-06-10 22:34:31 +00:00
Eric Christopher 1f8ad4f4a7 Move X86RegisterInfo away from using the TargetMachine and only
using the subtarget.

llvm-svn: 210595
2014-06-10 22:34:28 +00:00
Rafael Espindola f5d07fa586 Mark a few functions noexcept.
This reduces the difference between std::error_code and llvm::error_code.

llvm-svn: 210591
2014-06-10 21:26:47 +00:00
Eric Christopher 68d7559e97 Use the TargetMachine on the DAG or the MachineFunction instead
of using the cached TargetMachine.

llvm-svn: 210589
2014-06-10 21:25:13 +00:00
Tom Stellard 4e07b1d76b R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210588
2014-06-10 21:20:41 +00:00
Tom Stellard 060ae39022 R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210587
2014-06-10 21:20:38 +00:00
Eric Christopher 2af33756c7 We already have a reference to the TargetMachine, use that.
llvm-svn: 210580
2014-06-10 20:39:39 +00:00
Eric Christopher 576d36ae05 Have isInTailCallPosition take the DAG so that we can use the
version of TargetLowering/Machine from there on the way to avoiding
TargetMachine in TargetLowering.

llvm-svn: 210579
2014-06-10 20:39:38 +00:00
Eric Christopher 09fc276d08 Reorder includes to be sorted.
llvm-svn: 210578
2014-06-10 20:39:35 +00:00
Reid Kleckner b01961c2c1 Revert "Patch by Ray Donnelly to print register names instead of numbers."
This reverts commit r206683.

The code was confusing SEH register numbers with DWARF register numbers.
The test case it was committed with was obviously incorrect.  The
disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg
%rbp', and other exciting things.

Noticed by Vadim Chugunov.

llvm-svn: 210574
2014-06-10 20:16:36 +00:00
Matt Arsenault a73fd935d8 Fix error in tablegen when either operand of !if is an empty list.
!if([Something], []) would error with "No type for list".

llvm-svn: 210572
2014-06-10 20:10:08 +00:00
Eric Christopher db5028bd5b Fix typos.
llvm-svn: 210571
2014-06-10 20:07:29 +00:00
Matt Arsenault 6042506b5c R600: Use BCNT_INT for evergreen
llvm-svn: 210569
2014-06-10 19:18:28 +00:00
Matt Arsenault 8333e4378e R600/SI: Implement i64 ctpop
llvm-svn: 210568
2014-06-10 19:18:24 +00:00
Matt Arsenault b5b5110b5c R600/SI: Use bcnt instruction for ctpop
llvm-svn: 210567
2014-06-10 19:18:21 +00:00
Matt Arsenault 6e43965fbc R600: Handle fcopysign
llvm-svn: 210564
2014-06-10 19:00:20 +00:00
Matt Arsenault b2cbf799d1 R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
llvm-svn: 210563
2014-06-10 18:54:59 +00:00
Eric Christopher 19b1d73e88 Add a FIXME.
llvm-svn: 210559
2014-06-10 18:31:18 +00:00
Eric Christopher fcb06ca908 Move AArch64SelectionDAGInfo down to the subtarget.
llvm-svn: 210557
2014-06-10 18:21:53 +00:00
Juergen Ributzka 89fe23e888 [FastISel] Collect statistics about failing intrinsic calls.
Add more instruction-specific statistics about failing intrinsic calls during
FastISel.

llvm-svn: 210556
2014-06-10 18:17:00 +00:00
Eric Christopher 17254eea62 Remove the cached little endian variable. We can get it easily off
of the DataLayout.

llvm-svn: 210555
2014-06-10 18:11:20 +00:00
Eric Christopher 078a2b62ab Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.

llvm-svn: 210554
2014-06-10 18:06:28 +00:00
Eric Christopher 57c2319bb3 Remove caching of the subtarget for AArch64SelectionDAGInfo.
llvm-svn: 210553
2014-06-10 18:06:25 +00:00
Eric Christopher 6f2a203f24 Move DataLayout onto the AArch64 subtarget.
llvm-svn: 210552
2014-06-10 18:06:23 +00:00
Zachary Turner a40ccf620b Test commit, wraps some lines to fit in 80 columns.
llvm-svn: 210551
2014-06-10 18:03:04 +00:00
Eric Christopher 29aab7b355 Move AArch64FrameLowering into the subtarget.
llvm-svn: 210549
2014-06-10 17:44:12 +00:00
Eric Christopher bc76b97797 Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.

llvm-svn: 210548
2014-06-10 17:33:39 +00:00
Reed Kotler 063d4fba36 Do Materialize Floating Point in Mips Fast-Isel
Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

llvm-svn: 210546
2014-06-10 16:45:44 +00:00
Andrea Di Biagio fa508af0fe [X86] Improved target combine rules for selecting horizontal add/sub.
This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for 
the VEX.256 encoded versions of horizontal add/sub.

For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.

Added a new test case into haddsub-2.ll.

llvm-svn: 210545
2014-06-10 16:42:57 +00:00
Tom Stellard d172270c44 Hexagon: Expand i1 SELECT_CC
il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.

llvm-svn: 210544
2014-06-10 16:42:41 +00:00
Adam Nemet 7f62b23e92 [X86] AVX512: Add vmovntdqa
Along with the corresponding intrinsic and tests.

llvm-svn: 210543
2014-06-10 16:39:53 +00:00
Renato Golin 65eea557ae Fix a bug in the Thumb1 ARM Load/Store optimizer
Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.

This patch fixes PR19972. Patch by Moritz Roth.

llvm-svn: 210542
2014-06-10 16:39:21 +00:00
Tom Stellard 3787b12255 SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC
The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:

setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);

to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.

llvm-svn: 210541
2014-06-10 16:01:29 +00:00
Tom Stellard b9a023383e SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
This prevents a future commit from regressing:

test/CodeGen/R600/setcc-equivalent.ll

llvm-svn: 210540
2014-06-10 16:01:25 +00:00
Tom Stellard 3ca1bfc728 SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

llvm-svn: 210539
2014-06-10 16:01:22 +00:00
Bill Schmidt f910a0650e [PPC64LE] Recognize shufflevector patterns for little endian
Various masks on shufflevector instructions are recognizable as
specific PowerPC instructions (vector pack, vector merge, etc.).
There is existing code in PPCISelLowering.cpp to recognize the correct
patterns for big endian code.  The masks for these instructions are
different for little endian code due to the big-endian numbering
employed by these instructions.  This patch adds the recognition code
for little endian.

I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for
this.  The existing recognizer test (vec_shuffle.ll) is unnecessarily
verbose and difficult to read, so I felt it was better to add a new
test rather than modify the old one.

llvm-svn: 210536
2014-06-10 14:35:01 +00:00
Chad Rosier d863ae39d1 [AArch64] Emit .ident compiler version attribute.
Patch by Ana Pazos<apazos@codeaurora.org>!

llvm-svn: 210535
2014-06-10 14:32:08 +00:00
Artyom Skrobov 6c8682e2e9 Condition codes AL and NV are invalid in the aliases that use
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.

llvm-svn: 210528
2014-06-10 13:11:35 +00:00
Artyom Skrobov 8b98532af9 Anonymous definitions in foreach blocks triggered a 'def already exists'
llvm-svn: 210526
2014-06-10 12:41:14 +00:00
Tim Northover 9ffd0b020f AArch64: disallow x30 & x29 as the destination for indirect tail calls
As Ana Pazos pointed out, these have to be restored to their incoming values
before a function returns; i.e. before the tail call. So they can't be used
correctly as the destination register.

llvm-svn: 210525
2014-06-10 10:50:24 +00:00
Tim Northover 7b9f86da5d Revert "X86: elide comparisons after cmpxchg instructions."
This reverts commit r210523. It was committed prematurely without waiting for
review.

llvm-svn: 210524
2014-06-10 10:50:11 +00:00
Tim Northover 84ad29ca1f X86: elide comparisons after cmpxchg instructions.
The C++ and C semantics of the compare_and_swap operations actually
require us to return a boolean "success" value. In LLVM terms this
means a second comparison of the output of "cmpxchg" against the input
desired value.

However, x86's "cmpxchg" instruction sets all flags for the comparison
formed, so we can skip any secondary comparison. (N.b. this isn't true
for cmpxchg8b/16b, which only set ZF).

rdar://problem/13201607

llvm-svn: 210523
2014-06-10 10:49:07 +00:00
Tim Northover c141ad4b75 AArch64: teach FastISel how to handle offset FrameIndices
Previously we were abandonning the attempt, leading to some combination of
extra work (when selection of a load/store fails completely) and inferior code
(when this leads to a real memcpy call instead of inlining).

rdar://problem/17187463

llvm-svn: 210520
2014-06-10 09:52:44 +00:00
Tim Northover c19445d07a AArch64: make FastISel memcpy emission more robust.
We were hitting an assert if FastISel couldn't create the load or store we
requested. Currently this happens for large frame-local addresses, though
CodeGen could be improved there.

rdar://problem/17187463

llvm-svn: 210519
2014-06-10 09:52:40 +00:00
Eric Christopher 0fb16ab204 Delete X86JITInfo in the subtarget destructor.
llvm-svn: 210516
2014-06-10 08:03:42 +00:00
Juergen Ributzka b2e4edb5c8 [ConstantHoisting][X86] Improve the cost model for small constants with large types (i64 and above).
This improves the X86 cost model for small constants with large types. Before
this commit we would even hoist trivial constants such as i96 2.

This is related to <rdar://problem/17070936>

llvm-svn: 210504
2014-06-10 00:32:29 +00:00
Reid Kleckner 16bf89ecb2 Reorder Value and User fields to save 8 bytes of padding on 64-bit
Reviewered by: rafael

Differential Revision: http://reviews.llvm.org/D4073

llvm-svn: 210501
2014-06-09 23:32:20 +00:00
Richard Trieu a23043cb9c Removing an "if (!this)" check from two print methods. The condition will
never be true in a well-defined context.  The checking for null pointers
has been moved into the caller logic so it does not rely on undefined behavior.

llvm-svn: 210497
2014-06-09 22:53:16 +00:00
Bill Schmidt 6b5a7dfc24 [PPC64LE] Generate correct code for unaligned little-endian vector loads
The code in PPCTargetLowering::PerformDAGCombine() that handles
unaligned Altivec vector loads generates a lvsl followed by a vperm.
As we've seen in numerous other places, the vperm instruction has a
big-endian bias, and this is fixed for little endian by complementing
the permute control vector and swapping the input operands.  In this
case the lvsl is providing the permute control vector.  Rather than
generating an lvsl and a complement operation, it is sufficient to
generate an lvsr instruction instead.  Thus for LE code generation we
will generate an lvsr rather than an lvsl, and swap the other input
arguments on the vperm.

The existing test/CodeGen/PowerPC/vec_misalign.ll is updated to test
the code generation for PPC64 and PPC64LE, in addition to the existing
PPC32/G5 testing.

llvm-svn: 210493
2014-06-09 22:00:52 +00:00
Alexey Samsonov 8000e2734e Generate better location ranges for some register-described variables.
Don't terminate location ranges for register-described variables
at the end of machine basic block if this register is never modified
in the function body, except for the prologue and epilogue. Prologue
location is guessed by FrameSetup flags on MachineInstructions, while
epilogue location is deduced from debug locations of instructions
in the basic blocks ending with return instructions.

This patch is mostly targeted to fix non-trivial debug locations for
variables addressed via stack and frame pointers.

It is not really a generic fix. We can still produce poor debug info
for register-described variables if this register *is* modified somewhere
in the function, but in unrelated places. This might be the case for the debug
info in optimized binaries (e.g. for local variables in inlined functions).
LiveDebugVariables pass in CodeGen attempts to fix this problem by adjusting
DBG_VALUE instructions, but this pass is tied to greedy register allocator,
which is used in optimized builds only. Proper fix would likely involve
generalizing LiveDebugVariables to all register allocators. See more discussion
in http://reviews.llvm.org/D3933 review thread.

I'm proceeding with this patch to fix immediate severe problems and
important cases, e.g. fix completely broken debug info with AddressSanitizer
and fix PR19307 (missing debug info for by-value std::string arguments).

llvm-svn: 210492
2014-06-09 21:53:47 +00:00
Saleem Abdulrasool abac6e92a0 ARM: add VLA extension for WoA Itanium ABI
The armv7-windows-itanium environment is nearly identical to the MSVC ABI. It
has a few divergences, mostly revolving around the use of the Itanium ABI for
C++. VLA support is one of the extensions that are amongst the set of the
extensions.

This adds support for proper VLA emission for this environment. This is
somewhat similar to the handling for __chkstk emission on X86 and the large
stack frame emission for ARM. The invocation style for chkstk is still
controlled via the -mcmodel flag to clang.

Make an explicit note that this is an extension.

llvm-svn: 210489
2014-06-09 20:18:42 +00:00
Matt Arsenault 44f60d0a60 Look through addrspacecasts when turning ptr comparisons into
index comparisons.

llvm-svn: 210488
2014-06-09 19:20:29 +00:00
Alp Toker 51420a8d62 Remove old fenv.h workaround for a historic clang driver bug
Tested and works fine with clang using libstdc++.

All indications are that this was fixed some time ago and isn't a problem with
any clang version we support.

I've added a note in PR6907 which is still open for some reason.

llvm-svn: 210485
2014-06-09 19:00:52 +00:00
Alp Toker c817d6a5b5 Fold FEnv.h into the implementation
Support headers shouldn't use config.h definitions, and they should never be
undefined like this.

ConstantFolding.cpp was the only user of this facility and already includes
config.h for other math features, so it makes sense to move the checks there at
point of use.

(The implicit config.h was also quite dangerous -- removing the FEnv.h include
would have silently disabled math constant folding without causing any tests to
fail. Need to investigate -Wundef once the cleanup is done.)

This eliminates the last config.h include from LLVM headers, paving the way for
more consistent configuration checks.

llvm-svn: 210483
2014-06-09 18:28:53 +00:00
Eric Christopher a08f30bd40 Move all of the x86 subtarget initialized variables down into the x86 subtarget
from the x86 target machine. Should be no functional change.

llvm-svn: 210479
2014-06-09 17:08:19 +00:00
Matt Arsenault 93840c095a R600/SI: Rename VOP3 helper class to be more general
It has other uses besides shift instructions.

llvm-svn: 210478
2014-06-09 17:00:46 +00:00
Andrea Di Biagio f99dd64f0a [X86] Add target combine rules for horizontal add/sub.
This patch adds new target specific combine rules to identify horizontal
add/sub idioms from BUILD_VECTOR dag nodes.

This patch also teaches the DAGCombiner how to canonicalize sequences of
insert_vector_elt dag nodes according to the following rule:

  (insert_vector_elt (insert_vector_elt A, I0), I1) ->
    (insert_vecto_elt (insert_vector_elt A, I1), I0)

This new canonicalization rule only triggers if the inner insert_vector
dag node has exactly one use; also, both indices must be known constants,
and I1 < I0.
This last rule made it possible to write a simpler algorithm to identify
horizontal add/sub patterns because now we don't have to worry about the
ordering of insert_vector_elt dag nodes.

llvm-svn: 210477
2014-06-09 16:54:41 +00:00
Matt Arsenault 689f325099 R600/SI: Keep 64-bit not on SALU
llvm-svn: 210476
2014-06-09 16:36:31 +00:00
Matt Arsenault 13ccc8f1bc R600: Fix selection failure for vector bswap
llvm-svn: 210475
2014-06-09 16:20:25 +00:00
Bill Schmidt 42995e8c74 [PPC64LE] Generate correct little-endian code for v16i8 multiply
The existing code in PPCTargetLowering::LowerMUL() for multiplying two
v16i8 values assumes that vector elements are numbered in big-endian
order.  For little-endian targets, the vector element numbering is
reversed, but the vmuleub, vmuloub, and vperm instructions still
assume big-endian numbering.  To account for this, we must adjust the
permute control vector and reverse the order of the input registers on
the vperm instruction.

The existing test/CodeGen/PowerPC/vec_mul.ll is updated to be executed
on powerpc64 and powerpc64le targets as well as the original powerpc
(32-bit) target.

llvm-svn: 210474
2014-06-09 16:06:29 +00:00
Evgeniy Stepanov 70d1b0a818 [msan] Workaround for invalid origins in shufflevector.
Makes origin propagation ignore literal undef operands, and,
in general, any operand we don't have origin for.

https://code.google.com/p/memory-sanitizer/issues/detail?id=56

llvm-svn: 210472
2014-06-09 14:29:34 +00:00
Sasa Stankovic e435f5b2d4 [mips] Fix a bug for NaCl target - Don't report the error when non-dangerous
load/store is in branch delay slot.

Differential Revision: http://llvm-reviews.chandlerc.com/D4048

llvm-svn: 210470
2014-06-09 14:09:28 +00:00
Andrea Di Biagio dfbdc71ea1 [X86] Avoid emitting unnecessary test instructions.
This patch teaches the backend how to check for the 'NoSignedWrap' flag on
binary operations to improve the emission of 'test' instructions.

If the result of a binary operation is known not to overflow we know that
resetting the Overflow flag is unnecessary and so we can avoid emitting
the test instruction.

Patch by Marcello Maggioni.

llvm-svn: 210468
2014-06-09 12:34:50 +00:00
Andrea Di Biagio 4db1abea15 [DAG] Expose NoSignedWrap, NoUnsignedWrap and Exact flags to SelectionDAG.
This patch modifies SelectionDAGBuilder to construct SDNodes with associated
NoSignedWrap, NoUnsignedWrap and Exact flags coming from IR BinaryOperator
instructions.

Added a new SDNode type called 'BinaryWithFlagsSDNode' to allow accessing
nsw/nuw/exact flags during codegen.

Patch by Marcello Maggioni.

llvm-svn: 210467
2014-06-09 12:32:53 +00:00
Alexey Volkov 5260dba323 [X86] Use ADD/SUB instead of INC/DEC for Silvermont
According to Intel Software Optimization Manual 
on Silvermont INC or DEC instructions require 
an additional uop to merge the flags.
As a result, a branch instruction depending 
on an INC or a DEC instruction incurs a 1 cycle penalty.

Differential Revision: http://reviews.llvm.org/D3990

llvm-svn: 210466
2014-06-09 11:40:41 +00:00
Artyom Skrobov 82ae94f704 [AArch64] Missing aliases for CMP/CMN [W]SP with no shift
llvm-svn: 210464
2014-06-09 11:10:14 +00:00
Zoran Jovanovic 2855142ac5 [mips][mips64r6] Add LDPC instruction
Differential Revision: http://reviews.llvm.org/D3822

llvm-svn: 210460
2014-06-09 09:49:51 +00:00
Evgeniy Stepanov 2be29929be Fix line numbers for code inlined from __nodebug__ functions.
Instructions from __nodebug__ functions don't have file:line
information even when inlined into no-nodebug functions. As a result,
intrinsics (SSE and other) from <*intrin.h> clang headers _never_
have file:line information.

With this change, an instruction without !dbg metadata gets one from
the call instruction when inlined.

Fixes PR19001.

llvm-svn: 210459
2014-06-09 09:09:19 +00:00
Evgeniy Stepanov f7c29a9e25 [msan] Fix vector pack intrinsic handling.
This fixes a crash on MMX intrinsics, as well as a corner case in handling of
all unsigned pack intrinsics.

PR19953.

llvm-svn: 210454
2014-06-09 08:40:16 +00:00
Patrik Hagglund aad35e7fc4 Fix gcc warning (enumeral and non-enumeral type in conditional expression)
llvm-svn: 210450
2014-06-09 07:35:07 +00:00
Chad Rosier 3fe0c876c4 [AArch64] Fix the ordering of the accumulate operand in SchedRW list.
Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

llvm-svn: 210446
2014-06-09 01:54:00 +00:00
Chad Rosier d96e9f14ee [AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift
plus add.  The shift can be folded into the add.  This only effects codegen
when the constant is 3.

llvm-svn: 210445
2014-06-09 01:25:51 +00:00