Commit Graph

340457 Commits

Author SHA1 Message Date
Craig Topper d3bf06bc81 [DAGCombiner] Add combine for (not (strict_fsetcc)) to create a strict_fsetcc with the opposite condition.
Unlike the existing code that I modified here, I only handle the
case where the strict_fsetcc has a single use. Not sure exactly
how to handle multiples uses.

Testing this on X86 is hard because we already have a other
combines that get rid of lowered version of the integer setcc that
this xor will eventually become. So this combine really just
saves a bunch of extra nodes being created. Not sure about other
targets.

Differential Revision: https://reviews.llvm.org/D71816
2020-01-24 14:15:36 -08:00
shafik 118efa5cda [LLDB][NFC] Adding clarifying comment in SymbolFileDWARFDebugMap::DumpClangAST(...)
It is not obvious that the code was correct since it would seem as if we want to perform the dump for
each symbol file.
2020-01-24 14:01:15 -08:00
Evandro Menezes 9fa0f236d5 [PATCH] [Target] Test commit
Modify comment to reflect the current users of `Regisgter.CostPerUse`.
2020-01-24 15:56:08 -06:00
Evgenii Stepanov 596d06145a [GWP-ASan] enable/disable and fork support.
Summary:
* Implement enable() and disable() in GWP-ASan.
* Setup atfork handler.
* Improve test harness sanity and re-enable GWP-ASan in Scudo.

Scudo_standalone disables embedded GWP-ASan as necessary around fork().
Standalone GWP-ASan sets the atfork handler in init() if asked to. This
requires a working malloc(), therefore GWP-ASan initialization in Scudo
is delayed to the post-init callback.

Test harness changes are about setting up a single global instance of
the GWP-ASan allocator so that pthread_atfork() does not create
dangling pointers.

Test case shamelessly stolen from D72470.

Reviewers: cryptoad, hctim, jfb

Subscribers: mgorny, jfb, #sanitizers, llvm-commits

Tags: #sanitizers, #llvm

Differential Revision: https://reviews.llvm.org/D73294
2020-01-24 13:53:26 -08:00
LLVM GN Syncbot da8bada938 [gn build] Port 8a81daaa8b 2020-01-24 21:42:43 +00:00
Reid Kleckner 8a81daaa8b [AST] Split parent map traversal logic into ParentMapContext.h
The only part of ASTContext.h that requires most AST types to be
complete is the parent map. Nothing in Clang proper uses the ParentMap,
so split it out into its own class. Make ASTContext own the
ParentMapContext so there is still a one-to-one relationship.

After this change, 562 fewer files depend on ASTTypeTraits.h, and 66
fewer depend on TypeLoc.h:
  $ diff -u deps-before.txt deps-after.txt | \
    grep '^[-+] ' | sort | uniq -c | sort -nr | less
      562 -    ../clang/include/clang/AST/ASTTypeTraits.h
      340 +    ../clang/include/clang/AST/ParentMapContext.h
       66 -    ../clang/include/clang/AST/TypeLocNodes.def
       66 -    ../clang/include/clang/AST/TypeLoc.h
       15 -    ../clang/include/clang/AST/TemplateBase.h
  ...
I computed deps-before.txt and deps-after.txt with `ninja -t deps`.

This removes a common and key dependency on TemplateBase.h and
TypeLoc.h.

This also has the effect of breaking the ParentMap RecursiveASTVisitor
instantiation into its own file, which roughly halves the compilation
time of ASTContext.cpp (29.75s -> 17.66s). The new file takes 13.8s to
compile.

I left behind forwarding methods for getParents(), but clients will need
to include a new header to make them work:
  #include "clang/AST/ParentMapContext.h"

I noticed that this parent map functionality is unfortunately duplicated
in ParentMap.h, which only works for Stmt nodes.

Reviewed By: rsmith

Differential Revision: https://reviews.llvm.org/D71313
2020-01-24 13:42:28 -08:00
Craig Topper b1f3a0f972 Revert a107f86 "[GlobalsAA] Add back a check to intrinsic_addresstaken.ll to see if the AVX and AVX512 bots still fail for it."
It still fails some buildbots which is what I was trying to test.
2020-01-24 13:15:23 -08:00
Matt Arsenault 3b93945587 AMDGPU/GlobalISel: Select wqm, softwqm and wwm intrinsics 2020-01-24 13:06:44 -08:00
Matt Arsenault 87c46a3129 AMDGPU: Don't error on ds.ordered intrinsic in function
These should be assumed to be called from a compute context. Also
don't use a 2 entry switch over constants.
2020-01-24 13:06:44 -08:00
LLVM GN Syncbot 36b887ed15 [gn build] Port 3f8b100e94 2020-01-24 21:02:26 +00:00
Dmitry Polukhin 3f8b100e94 [clang-tidy] Add library for clang-tidy main function
Summary:
This library allows to create clang-tidy tools with custom checks outside of llvm repo
using prebuilt clang release tarball.

Test Plan:
Checked that clang-tidy works as before. New library exists in istall dir.

Reviewers: smeenai, gribozavr, stephanemoore

Subscribers: mgorny, xazax.hun, cfe-commits

Tags: #clang-tools-extra, #clang

Differential Revision: https://reviews.llvm.org/D73300
2020-01-24 13:00:45 -08:00
Stanislav Mekhanoshin be8e38cbd9 Correct NumLoads in clustering
Scheduler sends NumLoads argument into shouldClusterMemOps()
one less the actual cluster length. So for 2 instructions
it will pass just 1. Correct this number.

This is NFC for in tree targets.

Differential Revision: https://reviews.llvm.org/D73292
2020-01-24 12:45:28 -08:00
Matt Arsenault 9c346464c1 TableGen/GlobalISel: Handle non-leaf EXTRACT_SUBREG
This previously only handled EXTRACT_SUBREGs from leafs, such as
operands directly in the original output. Handle extracting from a
result instruction.
2020-01-24 12:15:10 -08:00
Matt Arsenault d8328c0b62 TableGen: Work around assert on Mips register definitions
This would hit the "Biggest class wasn't first" assert in
getMatchingSubClassWithSubRegs in a future patch for EXTRACT_SUBREG
handling.

Mips defines 4 identical register classes (MSA128B, MSA128H, MSA128BW,
MSA128D). These have the same set of registers, and only differ by the
isel type. I believe this is an ill formed way of defining registers,
that probably is just to work around the inconvenience of mixing
different types in a single register class in DAG patterns.

Since these all have the same size, they would all sort to the
beginning, but you would not necessarily get the same super register
at the front as the assert enforces. Breaking the ambiguity by also
sorting by name doesn't work, since each of these register classes all
want to be first. Force sorting of the original register class if the
size is the same.
2020-01-24 12:15:10 -08:00
Matt Arsenault 84e035d8f1 AMDGPU: Don't check constant address space for atomic stores
We define a separate list for storable address spaces. This saves
entry in the matcher table address space list.
2020-01-24 12:15:09 -08:00
Matt Arsenault 4fdae24733 AMDGPU/GlobalISel: Add selection tests for G_ATOMICRMW_ADD 2020-01-24 12:15:09 -08:00
Craig Topper a107f86417 [GlobalsAA] Add back a check to intrinsic_addresstaken.ll to see if the AVX and AVX512 bots still fail for it.
These bots failed for this several months ago and as a result, this
check was removed. If they still fail I'm going to try to see if I
can figure out why.
2020-01-24 11:54:23 -08:00
Dimitry Andric 58592f6c49 Include <cstdlib> for std::abort() in clangd
This fixes a "not a member of 'std'" error with e.g. Fedora 32.

Closes: #105
2020-01-24 20:52:37 +01:00
LLVM GN Syncbot 6530136fe3 [gn build] Port 555d8f4ef5 2020-01-24 19:37:54 +00:00
Hans Wennborg 698d1cd3b8 Make address-space-lambda.cl pass on 32-bit Windows
Member functions will have the thiscall attribute on them.
2020-01-24 20:35:25 +01:00
Stanislav Mekhanoshin 555d8f4ef5 [AMDGPU] Bundle loads before post-RA scheduler
We are relying on atrificial DAG edges inserted by the
MemOpClusterMutation to keep loads and stores together in the
post-RA scheduler. This does not work all the time since it
allows to schedule a completely independent instruction in the
middle of the cluster.

Removed the DAG mutation and added pass to bundle already
clustered instructions. These bundles are unpacked before the
memory legalizer because it does not work with bundles but also
because it allows to insert waitcounts in the middle of a store
cluster.

Removing artificial edges also allows a more relaxed scheduling.

Differential Revision: https://reviews.llvm.org/D72737
2020-01-24 11:33:38 -08:00
Andy Kaylor b35b7da460 [PGO] Attach appropriate funclet operand bundles to value profiling instrumentation calls
Patch by Chris Chrulski

When generating value profiling instrumentation, ensure the call gets the
correct funclet token, otherwise WinEHPrepare will turn the call (and all
subsequent instructions) into unreachable.

Differential Revision: https://reviews.llvm.org/D73221
2020-01-24 11:20:53 -08:00
Stanislav Mekhanoshin 44b865fa7f [AMDGPU] Allow narrowing muti-dword loads
Currently BE allows only a little load narrowing because
of the fear it will produce sub-dword ext loads. However,
we can always allow narrowing if we are shrinking one
multi-dword load to another multi-dword load.

In particular we were unable to reduce s_load_dwordx8 into
s_load_dwordx4 if identity shuffle was used to extract
low 4 dwords.

Differential Revision: https://reviews.llvm.org/D73133
2020-01-24 11:03:41 -08:00
Stanislav Mekhanoshin 7a94d4f4ee Allow combining of extract_subvector to extract element
Differential Revision: https://reviews.llvm.org/D73132
2020-01-24 10:50:26 -08:00
Austin Kerbow c226646337 Resubmit: [DA][TTI][AMDGPU] Add option to select GPUDA with TTI
Summary:
Enable the new diveregence analysis by default for AMDGPU.

Resubmit with test updates since GPUDA was causing failures on Windows.

Reviewers: rampitec, nhaehnle, arsenm, thakis

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73315
2020-01-24 10:39:40 -08:00
Yuta Saito c5bd3d0726 Support Swift calling convention for WebAssembly targets
This adds basic support for the Swift calling convention with WebAssembly
targets.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D71823
2020-01-24 10:30:46 -08:00
Austin Kerbow 37aa16ebb7 [DA] Don't propagate from unreachable blocks
Summary: Fixes crash that could occur when a divergent terminator has an unreachable parent.

Reviewers: rampitec, nhaehnle, arsenm

Subscribers: jvesely, wdng, hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73323
2020-01-24 10:28:11 -08:00
David Zarzycki 5dda92fcb0
Add test for spaceship operator to __config
Summary:
The libcxx test suite auto-detects spaceship operator, but __config does not. This means that the libcxx test suite has been broken for over a month when using top-of-tree clang. This also really ought to be fixed before 10.0.

See: bc633a42dd

Reviewers: chandlerc, mclow.lists, EricWF, ldionne, CaseyCarter

Reviewed By: EricWF

Subscribers: broadwaylamb, hans, dexonsmith, tstellar, llvm-commits, libcxx-commits

Tags: #libc, #llvm

Differential Revision: https://reviews.llvm.org/D72980
2020-01-24 13:27:22 -05:00
Simon Pilgrim abd1927d44 Fix some comment typos. NFC. 2020-01-24 18:18:42 +00:00
Alina Sbirlea 0d90d2457c [LoopStrengthReduce] Teach LoopStrengthReduce to preserve MemorySSA is available. 2020-01-24 10:13:52 -08:00
Andy Kaylor a33accde95 [PGO] Early detection regarding whether pgo counter promotion is possible
Patch by Chris Chrulski

This fixes a problem with the current behavior when assertions are enabled.
A loop that exits to a catchswitch instruction is skipped for the counter
promotion, however this check was being done after the PGOCounterPromoter
tried to collect an insertion point for the exit block. A call to
getFirstInsertionPt() on a block that begins with a catchswitch instruction
triggers an assertion. This change performs a check whether the counter
promotion is possible prior to collecting the ExitBlocks and InsertPts.

Differential Revision: https://reviews.llvm.org/D73222
2020-01-24 09:55:41 -08:00
Fangrui Song 50a3ff30e1 [PatchableFunction] Allow empty entry MachineBasicBlock
Reviewed By: nickdesaulniers

Differential Revision: https://reviews.llvm.org/D73301
2020-01-24 09:42:48 -08:00
David Zarzycki 0d61cd25a6
Verify that clang's max alignment is <= LLVM's max alignment
Reviewers: lebedev.ri

Reviewed By: lebedev.ri

Subscribers: cfe-commits

Tags: #llvm, #clang

Differential Revision: https://reviews.llvm.org/D73363
2020-01-24 12:37:05 -05:00
David Green b535aa405a [ARM] Use reduction intrinsics for larger than legal reductions
The codegen for splitting a llvm.vector.reduction intrinsic into parts
will be better than the codegen for the generic reductions. This will
only directly effect when vectorization factors are specified by the
user.

Also added tests to make sure the codegen for larger reductions is OK.

Differential Revision: https://reviews.llvm.org/D72257
2020-01-24 17:07:24 +00:00
Fangrui Song f1dab29908 [ELF][PowerPC] Support R_PPC_COPY and R_PPC64_COPY
Reviewed By: Bdragon28, jhenderson, grimar, sfertile

Differential Revision: https://reviews.llvm.org/D73255
2020-01-24 09:06:20 -08:00
Kazushi (Jam) Marukawa 0fca35c652 [VE] global variable isel patterns
Summary: Asm expr fixups, isel patterns and tests for global variables addresses.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73355
2020-01-24 17:35:14 +01:00
Tom Weaver f5147765ba [DebugInfo][LiveDebugValues] Teach Live Debug Values About Meta Instructions
Previously LiveDebugValues pass would consider meta instructions that 'fiddle' with liveness of registers as register definitions when transfering register defs. This would mean that, for example, a KILL instruction would cause LiveDebugValues to terminate the range of an earlier DBG_VALUE instruction resulting in the none propogation of said DBG_VALUE instructions into later blocks.

This patch adds the check and a helpful comment, fixes a test that previously tested for the broken behaviour by coincidence and adds a test specifically for this.

reviewers: vsk, dstenb, djtodoro

Differential Revision: https://reviews.llvm.org/D73210
2020-01-24 16:29:05 +00:00
Artem Dergachev 1484d0f12a [analyzer] PthreadLock: Implement dead region cleanup.
Differential Revision: https://reviews.llvm.org/D37963
2020-01-24 18:43:24 +03:00
Artem Dergachev dd22be1e3d [analyzer] PthreadLock: Implement mutex escaping.
Differential Revision: https://reviews.llvm.org/D37812
2020-01-24 18:43:24 +03:00
Artem Dergachev 152bc7ffdc [analyzer] NFC: PthreadLock: Use CallDescriptionMap, modernize.
https://reviews.llvm.org/D37809
2020-01-24 18:43:23 +03:00
Artem Dergachev 15624a7bda [analyzer] PthreadLock: Add more XNU rwlock unlock functions.
Differential Revision: https://reviews.llvm.org/D37807
2020-01-24 18:43:23 +03:00
Artem Dergachev 80fd37f9d6 [analyzer] PthreadLock: Fix return value modeling for XNU lock functions.
Differential Revision: https://reviews.llvm.org/D37806
2020-01-24 18:43:23 +03:00
Simon Pilgrim 3fd5d1c6e7 [X86][SSE] combineTargetShuffle - permilps(shufps(load(),x)) --> permilps(shufps(x,load()))
Moves lowerShuffleWithSHUFPS commutation code from rG30fcd29fe479 to catch cases during combine
2020-01-24 15:23:20 +00:00
Roman Lebedev a8c3608a27
[Sema] Provide declarations for MaximumAlignment, MaxAlignmentExponent variables
clang-armv7-linux-build-cache bot is complaining about undefined
references to these variables during linking, so by explicitly
placing them in some TU we should be able to fix that.
2020-01-24 18:18:15 +03:00
Sergey Dmitriev f69eba0772 [llvm-objcopy][COFF] Add support for --set-section-flags
Reviewers: jhenderson, MaskRay, alexshap, rupprecht, mstorsjo

Reviewed By: jhenderson

Subscribers: abrachet, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73107
2020-01-24 07:12:55 -08:00
Sam McCall 76fa5d50f3 [clangd] Remove pesky ;. NFC 2020-01-24 16:12:00 +01:00
Sam McCall 6ef1ccecf7 [clangd] Rename DiagnosticsConsumer -> ClangdServer::Callbacks, and make it optional
Summary:
This reflects its current function better and avoids confusion with clang::DiagnosticConsumer.

The old name/constructor is left around temporarily for compatibility.
(Metagame: merging with out-of-tree changes is harder than usual this month)

Reviewers: hokein

Subscribers: ilya-biryukov, javed.absar, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D73346
2020-01-24 15:59:32 +01:00
Roman Lebedev 1d0972ff5e
[Sema] Introduce MaximumAlignment value, to be used instead of magical constants
There is llvm::Value::MaximumAlignment, which is numerically
equivalent to these constants, but we can't use it directly
because we can't include llvm IR headers in clang Sema.
So instead, copy-paste the constant, and fixup the places to use it.

This was initially reviewed in https://reviews.llvm.org/D72998
2020-01-24 17:49:17 +03:00
Kazushi (Jam) Marukawa 08ebd8c79e [VE] aligned load/store isel patterns
Summary:
Aligned load/store isel patterns and tests for
i1/i8/16/32/64 (including extension and truncation) and fp32/64.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D73276
2020-01-24 15:16:54 +01:00
Thomas Preud'homme 8e96697c7d FileCheck [9/12]: Add support for matching formats
Summary:
This patch is part of a patch series to add support for FileCheck
numeric expressions. This specific patch adds support for selecting a
matching format to match a numeric value against (ie. decimal, hex lower
case letters or hex upper case letters).

This commit allows to select what format a numeric value should be
matched against. The following formats are supported: decimal value,
lower case hex value and upper case hex value. Matching formats impact
both the format of numeric value to be matched as well as the format of
accepted numbers in a definition with empty numeric expression
constraint.

Default for absence of format is decimal value unless the numeric
expression constraint is non null and use a variable in which case the
format is the one used to define that variable. Conclict of format in
case of several variable being used is diagnosed and forces the user to
select a matching format explicitely.

This commit also enables immediates in numeric expressions to be in any
radix known to StringRef's GetAsInteger method, except for legacy
numeric expressions (ie [[@LINE+<offset>]] which only support decimal
immediates.

Copyright:
    - Linaro (changes up to diff 183612 of revision D55940)
    - GraphCore (changes in later versions of revision D55940 and
                 in new revision created off D55940)

Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar, arichardson

Reviewed By: jhenderson, arichardson

Subscribers: daltenty, MaskRay, hiraditya, llvm-commits, probinson, dblaikie, grimar, arichardson, kristina, hfinkel, rogfer01, JonChesterfield

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60389
2020-01-24 14:15:28 +00:00