Commit Graph

308430 Commits

Author SHA1 Message Date
Sanjay Patel 21aa6ddc14 [x86] narrow a shuffle that doesn't use or set any high elements
This isn't the final fix for our reduction/horizontal codegen, but it takes care 
of a lot of the problems. After we narrow the shuffle, existing combines for 
insert/extract and binops kick in, and we end up with cheaper 128-bit ops.

The avg and mul reduction tests show an existing shuffle lowering hole for 
AVX2/AVX512. I think in its most minimal form this is:
https://bugs.llvm.org/show_bug.cgi?id=40434
...but we might need multiple fixes to get it right.

Differential Revision: https://reviews.llvm.org/D57156

llvm-svn: 352209
2019-01-25 15:37:42 +00:00
Clement Courbet b120127001 Revert r351954 "Add a value_type to ArrayRef."
This breaks arm self-hosted buildbots.

llvm-svn: 352206
2019-01-25 15:25:52 +00:00
Haojian Wu aa3ed5a983 [clangd] NFC: fix clang-tidy warnings.
Most are about llvm code style violation (found via
readability-identifier-naming check).

llvm-svn: 352205
2019-01-25 15:14:03 +00:00
Sam McCall 1e7491ea9c [JSON] Work around excess-precision issue when comparing T_Integer numbers.
Reviewers: bkramer

Subscribers: kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D57237

llvm-svn: 352204
2019-01-25 15:05:33 +00:00
Diogo N. Sampaio 12430bf60b [NFC][Clang] Add driver tests for sb and predres
Add tests that arguments for enabling/disabling
sb and predres are correctly being or not passed
by the driver.

Differential Revision: https://reviews.llvm.org/D57060

llvm-svn: 352203
2019-01-25 14:57:22 +00:00
Nico Weber e4ed82d674 gn build: Merge r352149
llvm-svn: 352202
2019-01-25 14:53:30 +00:00
Nico Weber 0c828ccc67 gn build: Revert r352200, commit message was wrong
llvm-svn: 352201
2019-01-25 14:52:50 +00:00
Nico Weber 74bb231b90 gn build: Merge r352148
llvm-svn: 352200
2019-01-25 14:50:14 +00:00
Alex Bradbury 38c4ec31cb [RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines
This target-independent code won't trigger for cases such as RV32FD where
custom SelectionDAG nodes are generated. These new tests demonstrate such
cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and
fabs.s selection patterns are actually exercised.

llvm-svn: 352199
2019-01-25 14:33:08 +00:00
Simon Pilgrim d6e1e3569c Fix line endings and trim trailing whitespace. NFCI.
llvm-svn: 352198
2019-01-25 14:29:57 +00:00
Haojian Wu 7852b7106a gitignore: ignore clangd index files.
Reviewers: kadircet

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, llvm-commits

Differential Revision: https://reviews.llvm.org/D57227

llvm-svn: 352197
2019-01-25 14:05:18 +00:00
Simon Pilgrim d41ccddda9 [X86] Add addcarry/subborrow combine tests
Show failure to simplify cases with zero op/flags

llvm-svn: 352196
2019-01-25 12:26:27 +00:00
James Henderson 759d5e6783 [llvm-symbolizer] Add switch to adjust addresses by fixed offset
If a stack trace or similar has a list of addresses from an executable
or DSO loaded at a variable address (e.g. due to ASLR), the addresses
will not directly correspond to the addresses stored in the object file.
If a user wishes to use llvm-symbolizer, they have to subtract the load
address from every address. This is somewhat inconvenient, especially as
the output of --print-address will result in the adjusted address being
listed, rather than the address coming from the stack trace, making it
harder to map results between the two.

This change adds a new switch to llvm-symbolizer --adjust-vma which
takes an offset, which is then used to automatically do this
calculation. The printed address remains the input address (allowing for
easy mapping), whilst the specified offset is applied to the addresses
when performing the lookup.

The switch is conceptually similar to llvm-objdump's new switch of the
same name (see D57051), which in turn mirrors a GNU switch. There is no
equivalent switch in addr2line.

Reviewed by: grimar

Differential Revision: https://reviews.llvm.org/D57151

llvm-svn: 352195
2019-01-25 11:49:21 +00:00
Max Kazantsev 7822d25de3 [NFC] One more crashing test on LoopSimplifyCFG
llvm-svn: 352194
2019-01-25 11:47:16 +00:00
Simon Pilgrim dea6174b0b Fix gcc -Wparentheses warning. NFCI.
llvm-svn: 352193
2019-01-25 11:38:40 +00:00
Simon Pilgrim 1f4b979483 Fix "control reaches end of non-void function" warning. NFCI.
llvm-svn: 352192
2019-01-25 11:36:51 +00:00
Simon Pilgrim cdf58092e4 Fix gcc -Wparentheses warning. NFCI.
llvm-svn: 352191
2019-01-25 11:34:58 +00:00
Max Kazantsev e5116e9b4a [NFC] Add failing test on LCSSA forming
llvm-svn: 352190
2019-01-25 11:32:21 +00:00
Diana Picus 8976ad12a9 [ARM GlobalISel] Support shifts for Thumb2
Same as ARM.

On this occasion we split some of the instruction select tests for more
complicated instructions into their own files, so we can reuse them for
ARM and Thumb mode. Likewise for the legalizer tests.

llvm-svn: 352188
2019-01-25 10:48:42 +00:00
Diana Picus 23628c7b05 [ARM GlobalISel] Remove rebase artifact from r351882. NFC
r351882 introduced some superfluous calls to mark G_INTTOPTR and
G_PTRTOINT as legal (looks like a rebase mishap). Remove them.

llvm-svn: 352187
2019-01-25 10:48:35 +00:00
Anton Korobeynikov e07d7d8bb6 Revert r352181 as it's breaking the bots
llvm-svn: 352186
2019-01-25 10:35:35 +00:00
Javed Absar a3e3d85286 [TblGen] Extend !if semantics through new feature !cond
This patch extends TableGen language with !cond operator.
Instead of embedding !if inside !if which can get cumbersome,
one can now use !cond.
Below is an example to convert an integer 'x' into a string:

    !cond(!lt(x,0) : "Negative",
          !eq(x,0) : "Zero",
          !eq(x,1) : "One,
          1        : "MoreThanOne")

Reviewed By: hfinkel, simon_tatham, greened
Differential Revision: https://reviews.llvm.org/D55758

llvm-svn: 352185
2019-01-25 10:25:25 +00:00
Haojian Wu 7a35bdb7ec [clangd] Log clang-tidy configuration, NFC
Summary: This is used for debugging purpose.

Reviewers: sammccall

Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, kadircet, cfe-commits

Differential Revision: https://reviews.llvm.org/D57057

llvm-svn: 352184
2019-01-25 10:14:27 +00:00
Haojian Wu c67dab5bd0 [clang-tidy] Add check for underscores in googletest names.
Summary: Adds a clang-tidy warning for underscores in googletest names.

Patch by Kar Epker!

Reviewers: hokein, alexfh, aaron.ballman

Reviewed By: hokein

Subscribers: Eugene.Zelenko, JonasToth, MyDeveloperDay, lebedev.ri, xazax.hun, mgorny, cfe-commits

Tags: #clang-tools-extra

Differential Revision: https://reviews.llvm.org/D56424

llvm-svn: 352183
2019-01-25 10:03:49 +00:00
Douglas Yung 914e838e63 [llvm-objcopy] Add support for -g as an alias for --strip-debug
This change adds an option -g to llvm-objcopy which is an alias for the existing option --strip-debug.

This fixes PR40003.

Reviewed by: alexshap

Differential Revision: https://reviews.llvm.org/D57217

llvm-svn: 352182
2019-01-25 09:57:20 +00:00
Anton Korobeynikov 56bf7b56dc Disable PIC/PIE for MSP430 target by default.
Relocatable code generation is meaningless on MSP430, as the platform is too small to use shared libraries.

Patch by Dmitry Mikushev!

Differential Revision: https://reviews.llvm.org/D56927

llvm-svn: 352181
2019-01-25 09:41:20 +00:00
Raphael Isemann 2a1f300bb5 Fix typo in ClangModulesDeclVendor [NFC]
llvm-svn: 352180
2019-01-25 09:28:48 +00:00
Simon Pilgrim d36f7730cd [llvm-mca][X86] Add missing shuffle tests
Match the coverage of test\CodeGen\X86\avx512-shuffle-schedule.ll so we can get rid of -print-schedule (and fix PR37160) without losing schedule tests

llvm-svn: 352179
2019-01-25 09:17:30 +00:00
Anton Korobeynikov 509d5c4a7d [MSP430] Fix absolute addressing mode printing in AsmPrinter
Align checks for absolute addressing mode with its current
implementation (SR is used as a base register).

This fixes https://bugs.llvm.org/show_bug.cgi?id=39993

Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D56785

llvm-svn: 352178
2019-01-25 09:14:05 +00:00
Anton Korobeynikov 58f6bc509b [MSP430] Ajust f32/f64 alignment according to MSP430 EABI
Patch by Kristina Bessonova!

Differential Revision: https://reviews.llvm.org/D57015

llvm-svn: 352177
2019-01-25 08:51:53 +00:00
Max Kazantsev 6f2a0c6827 [NFC] Add test with multiple loops
llvm-svn: 352176
2019-01-25 08:46:00 +00:00
Raphael Isemann 46508f6f11 Refactor HAVE_LIBCOMPRESSION and related code in GDBRemoteCommunication
Summary:
The field `m_decompression_scratch_type` is only used when `HAVE_LIBCOMPRESSION` is
defined, which caused a warning which I fixed in rLLDB350675 by just marking the variable as always used.

This patch fixes this in a better way by only defining the variable (and the related `m_decompression_scratch`
variable) when `HAVE_LIBCOMPRESSION` is defined. This also required changing the way we handle
`HAVE_LIBCOMPRESSION` works, as this was previously always defined on macOS within the source file
but not in the header. Now it's always defined from within our config header when CMake defines it or when
we are on macOS.

The field initialization was moved to the header to prevent that we have `#ifdef` within our initializer list.

Reviewers: #lldb, jasonmolenda, sgraenitz, labath

Reviewed By: labath

Subscribers: labath, beanz, mgorny, lldb-commits, dblaikie

Differential Revision: https://reviews.llvm.org/D57011

llvm-svn: 352175
2019-01-25 08:21:47 +00:00
Zi Xuan Wu 308a609c6e [PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts
Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support.

We'd use VSX float comparison instruction instead of non-vsx float comparison instruction 
if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and 
VSFRC correspondingly if VSX feature is opened.

If the target does not have corresponding VSX instruction comparison for some type, 
just copy VSX-related register to common float register class and use non-vsx comparison instruction.

Differential Revision: https://reviews.llvm.org/D57078

llvm-svn: 352174
2019-01-25 07:24:59 +00:00
Craig Topper 8de5abc4c8 [X86] Remove mask and passthru arguments from vpconflict builtins. Use select in IR instead.
llvm-svn: 352173
2019-01-25 07:08:22 +00:00
Craig Topper 6fd9af587a [X86] Add non-masked versions of vpconflict intrinsics so we can use a select in the header file in clang.
I'll remove and autoupgrade the old intrinsics in a future commit.

llvm-svn: 352172
2019-01-25 07:08:07 +00:00
Alex Bradbury 456d3798d6 [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
Follow the same custom legalisation strategy as used in D57085 for
variable-length shifts (see that patch summary for more discussion). Although
we may lose out on some late-stage DAG combines, I think this custom
legalisation strategy is ultimately easier to reason about.

There are some codegen changes in rv64m-exhaustive-w-insts.ll but they are all
neutral in terms of the number of instructions.

Differential Revision: https://reviews.llvm.org/D57096

llvm-svn: 352171
2019-01-25 05:11:34 +00:00
Max Kazantsev 38cd9acbb9 [LoopSimplifyCFG] Fix inconsistency in blocks in loop markup
2nd part of D57095 with the same reason, just in another place. We never
fold branches that are not immediately in the current loop, but this check
is missing in `IsEdgeLive` As result, it may think that the edge in subloop is
dead while it's live. It's a pessimization in the current stance.

Differential Revision: https://reviews.llvm.org/D57147
Reviewed By: rupprecht	

llvm-svn: 352170
2019-01-25 05:05:02 +00:00
Alex Bradbury 299d690a50 [RISCV] Custom-legalise 32-bit variable shifts on RV64
The previous DAG combiner-based approach had an issue with infinite loops
between the target-dependent and target-independent combiner logic (see
PR40333). Although this was worked around in rL351806, the combiner-based
approach is still potentially brittle and can fail to select the 32-bit shift
variant when profitable to do so, as demonstrated in the pr40333.ll test case.

This patch instead introduces target-specific SelectionDAG nodes for
SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a
good example of how this approach can improve codegen.

This adds DAG combine that does SimplifyDemandedBits on the operands (only
lower 32-bits of first operand and lower 5 bits of second operand are read).
This seems better than implementing SimplifyDemandedBitsForTargetNode as there
is no guarantee that would be called (and it's not for e.g. the anyext return
test cases). Also implements ComputeNumSignBitsForTargetNode.

There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new
instruction sequences are semantically equivalent.

Differential Revision: https://reviews.llvm.org/D57085

llvm-svn: 352169
2019-01-25 05:04:00 +00:00
Matt Arsenault 3b9a82ff2c AMDGPU/GlobalISel: Remove leftover setAction
Also move G_GEP actions together.

llvm-svn: 352168
2019-01-25 04:54:00 +00:00
Matt Arsenault 3e08b772b3 AMDGPU/GlobalISel: Scalarize add/sub
llvm-svn: 352167
2019-01-25 04:53:57 +00:00
Matt Arsenault e6cebd0d69 GlobalISel: fewerElementsVector for more cast types
llvm-svn: 352166
2019-01-25 04:37:33 +00:00
Matt Arsenault 95fd95cfe0 GlobalISel: fewerElementsVector for a few more trivial ops
llvm-svn: 352165
2019-01-25 04:03:38 +00:00
Matt Arsenault 5d622fbcc1 AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
llvm-svn: 352162
2019-01-25 03:23:04 +00:00
Vedant Kumar 9d70f2b939 [HotColdSplit] Describe the pass in more detail, NFC
llvm-svn: 352161
2019-01-25 03:22:38 +00:00
Vedant Kumar 65de025d64 [HotColdSplit] Split more aggressively before/after cold invokes
While a cold invoke itself and its unwind destination can't be
extracted, code which unconditionally executes before/after the invoke
may still be profitable to extract.

With cost model changes from D57125 applied, this gives a 3.5% increase
in split text across LNT+externals on arm64 at -Os.

llvm-svn: 352160
2019-01-25 03:22:23 +00:00
James Y Knight 5cf6665373 Define the _fltused symbol in one lldb test as well, post-r352076.
llvm-svn: 352159
2019-01-25 03:21:23 +00:00
Jason Molenda 9073eb4f25 Remove a warning in DynamicLoaderDarwin::UpdateImageLoadAddress
when the binary loaded in memory has a section that we cannot find
in the on-disk version.  I added this warning out of an overabundance
of caution originally, but I've never seen an instance of it being
hit in the past few years, and there are some changes for the shared
cache on darwin systems where a segment is added when the shared
cache is constructed so we're now hitting this warning.  I've decided
to remove it altogether.

<rdar://problem/46889346> 

llvm-svn: 352158
2019-01-25 03:01:48 +00:00
Matt Arsenault 1b1e685f10 GlobalISel: Support fewerElementsVector for icmp/fcmp
Also legalize 64-bit compares for AMDGPU

llvm-svn: 352157
2019-01-25 02:59:34 +00:00
Petr Hosek f16e834dab [AArch64] Make the test for rsr and rsr64 stricter
ACLE specifies that return type for rsr and rsr64 is uint32_t and
uint64_t respectively. D56852 change the return type of rsr64 from
unsigned long to unsigned long long which at least on Linux doesn't
match uint64_t, but the test isn't strict enough to detect that
because compiler implicitly converts unsigned long long to uint64_t,
but it breaks other uses such as printf with PRIx64 type specifier.
This change makes the test stricter enforcing that the return type
of rsr and rsr64 builtins is what is actually specified in ACLE.

Differential Revision: https://reviews.llvm.org/D57210

llvm-svn: 352156
2019-01-25 02:42:30 +00:00
Matt Arsenault ca676343a9 GlobalISel: Implement fewerElementsVector for extensions
llvm-svn: 352155
2019-01-25 02:36:32 +00:00